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    Multi-patterning method
    1.
    发明授权
    Multi-patterning method 有权
    多图案化方法

    公开(公告)号：US08473873B2

    公开(公告)日：2013-06-25

    申请号：US13224486

    申请日：2011-09-02

    申请人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    发明人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G03F1/70

    摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

    摘要翻译： 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

    MULTI-PATTERNING METHOD
    2.
    发明申请
    MULTI-PATTERNING METHOD 有权

    公开(公告)号：US20130061186A1

    公开(公告)日：2013-03-07

    申请号：US13224486

    申请日：2011-09-02

    申请人： Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    发明人： Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G03F1/70

    摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

    Tool and method for eliminating multi-patterning conflicts
    3.
    发明授权
    Tool and method for eliminating multi-patterning conflicts 有权
    消除多图案化冲突的工具和方法

    公开(公告)号：US08448100B1

    公开(公告)日：2013-05-21

    申请号：US13444158

    申请日：2012-04-11

    申请人： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

    发明人： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70

    摘要： A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

    摘要翻译： 计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。 专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

    MULTI-PATTERNING METHOD
    4.
    发明申请
    MULTI-PATTERNING METHOD 有权
    多图案方法

    公开(公告)号：US20130074018A1

    公开(公告)日：2013-03-21

    申请号：US13238127

    申请日：2011-09-21

    申请人： Chin-Chang HSU ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    发明人： Chin-Chang HSU ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70

    摘要： A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.

    摘要翻译： 一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接 图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

    Methodology for analysis and fixing guidance of pre-coloring layout
    5.
    发明授权
    Methodology for analysis and fixing guidance of pre-coloring layout 有权
    预先着色布局的分析和固定指导方法

    公开(公告)号：US08434043B1

    公开(公告)日：2013-04-30

    申请号：US13480847

    申请日：2012-05-25

    申请人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    发明人： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.

    摘要翻译： 本公开涉及一种用于识别预着色违规的方法和装置，并且用于向设计者提供提示和/或警告以消除预着色违规。 在一些实施例中，该方法通过识别具有多个预着色形状的集成芯片（IC）布局的双图案形成技术（DPT）层内的G0空间来执行。 基于G0空格识别在预色图案之间延伸的违规路径。 还识别出良好路径（即，不会引起违规的路径）和不良路径（即将导致违规的路径）。 提示和/或警告是基于所识别的好路径和不良路径生成的，其中提示和/或警告提供指导以消除违规路径并开发无违规IC布局。

    Multi-patterning method
    6.
    发明授权
    Multi-patterning method 有权
    多图案化方法

    公开(公告)号：US08468470B2

    公开(公告)日：2013-06-18

    申请号：US13238127

    申请日：2011-09-21

    申请人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    发明人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70

    摘要： A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.

    摘要翻译： 一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接 图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

    Decomposition and marking of semiconductor device design layout in double patterning lithography
    7.
    发明授权
    Decomposition and marking of semiconductor device design layout in double patterning lithography 有权
    半双工图案平版印刷中半导体器件设计布局的分解和标记

    公开(公告)号：US08775977B2

    公开(公告)日：2014-07-08

    申请号：US13027520

    申请日：2011-02-15

    申请人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

    发明人： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

    摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

    摘要翻译： 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。

    Routing system and method for double patterning technology
    8.
    发明授权
    Routing system and method for double patterning technology 有权
    双重图案化技术的路由系统和方法

    公开(公告)号：US08239806B2

    公开(公告)日：2012-08-07

    申请号：US12649979

    申请日：2009-12-30

    申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

    发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Gwan Sin Chang ,  Wen-Ju Yang ,  Zhe-Wei Jiang ,  Yi-Kan Cheng ,  Lee-Chung Lu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.

    摘要翻译： 一种方法包括接收要包括在IC布局中的多个电路部件的标识。 生成表示连接两个电路部件的第一图案的数据。 第一图案具有多个片段。 至少两个片段具有彼此垂直的纵向方向。 保留与至少两个段中的至少一个相邻的至少一个无图案区域。 生成表示在第一图案附近的一个或多个附加图案的数据。 在无模式区域中没有形成附加图案。 第一种图案和附加图案形成双重图案化顺应的图案集合。 将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。