公开(公告)号：US09553043B2

公开(公告)日：2017-01-24

申请号：US13438565

申请日：2012-04-03

申请人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Fang-Yu Fan ,  Yu-Hsiang Kao ,  Dian-Hau Chen ,  Shyue-Shyh Lin ,  Chii-Ping Chen

发明人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Fang-Yu Fan ,  Yu-Hsiang Kao ,  Dian-Hau Chen ,  Shyue-Shyh Lin ,  Chii-Ping Chen

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

摘要翻译： 一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。 互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。 互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。 所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。

公开(公告)号：US20140001638A1

公开(公告)日：2014-01-02

申请号：US13540464

申请日：2012-07-02

申请人： Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

发明人： Chung-Min Fu ,  Wen-Hao Chen ,  Dian-Hau Chen

IPC分类号： H01L23/50 ,  H01L21/306

CPC分类号： H01L21/768 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括工件和在金属化层中设置在工件上的多个第一导电线。 多个第二导线设置在金属化层中的工件上方。 多个第二导电线在工件的横截面视图中包括比多个第一导电线的垂直高度更大的垂直高度。

公开(公告)号：US08470263B2

公开(公告)日：2013-06-25

申请号：US13071578

申请日：2011-03-25

申请人： Chih-Hsin Shih ,  Hou-Jin Wu ,  Chih-Huong Yeh ,  Wen-Hao Chen ,  Kang-Yang Fan ,  Jin-Pin Hung

发明人： Chih-Hsin Shih ,  Hou-Jin Wu ,  Chih-Huong Yeh ,  Wen-Hao Chen ,  Kang-Yang Fan ,  Jin-Pin Hung

IPC分类号： G01N15/06 ,  G01N33/00 ,  G01N33/48

CPC分类号： B01L3/502738 ,  B01L2200/0621 ,  B01L2300/0803 ,  B01L2400/0409 ,  B01L2400/0688 ,  B01L2400/084 ,  Y10T137/877

摘要： A microfluidic device has a body, multiple channels, multiple reservoirs and multiple capillary valves. The reservoirs are formed on the body. Each channel is formed on the body and connects to a corresponding reservoir. The channels include a main channel and at least one branch channel. The main channel is formed on the top of the body and extends in a direction from the center to a circumference of the body. Each capillary valve is mounted on a corresponding channel and at a distance substantially close to the center of the body so differences between the burst frequencies of the capillary valves are increased. The microfluidic device has an excellent flow control on sequentially releasing fluid through distinct burst frequencies of microcapillary valves.

摘要翻译： 微流体装置具有主体，多通道，多个储存器和多个毛细管阀。 水箱形成在身上。 每个通道形成在主体上并连接到相应的储存器。 信道包括主信道和至少一个分支信道。 主通道形成在主体的顶部并且沿着从身体的中心到圆周的方向延伸。 每个毛细阀安装在相应的通道上并且基本上接近主体的中心的距离处，因此毛细血管的突发频率之间的差异增加。 微流体装置具有优良的流量控制，能够通过微毛细管阀的不同突发频率依次释放流体。

公开(公告)号：US08431968B2

公开(公告)日：2013-04-30

申请号：US12845162

申请日：2010-07-28

申请人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Shen-Feng Chen ,  Meng-Fu You

发明人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Shen-Feng Chen ,  Meng-Fu You

IPC分类号： H01L23/52

CPC分类号： G06F17/5077 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01L23/5286 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

公开(公告)号：US20110185331A1

公开(公告)日：2011-07-28

申请号：US12692184

申请日：2010-01-22

申请人： Dinesh Baviskar ,  Wen-Hao Chen ,  Chung-Sheng Yuan ,  Mark Shane Peng ,  Yun-Han Lee

发明人： Dinesh Baviskar ,  Wen-Hao Chen ,  Chung-Sheng Yuan ,  Mark Shane Peng ,  Yun-Han Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/78

摘要： A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

摘要翻译： 设计集成电路的方法包括提供包括电力网络的集成电路设计。 提供一种电压降缓解系统，其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。 添加了使用电压降缓解系统的用于电力网络的冗余带，其中冗余带将源节点和终端节点互连。 在添加冗余带的步骤之后，可以添加虚拟图案。

公开(公告)号：US20110006840A1

公开(公告)日：2011-01-13

申请号：US12772814

申请日：2010-05-03

申请人： Wen-Hao Chen

发明人： Wen-Hao Chen

IPC分类号： H01L25/00 ,  G06F17/50

CPC分类号： G06F17/5045

摘要： A method of forming an integrated circuit includes providing a first design of the integrated circuit; analyzing the first design to identify a first flip-flop having setup/hold violations and a second flip-flop not having setup/hold violations; and replacing the first flip-flop with a third flip-flop having a substantially same cell delay as the first flip-flop to form a second design of the integrated circuit. The first flip-flop and the third flip-flop have different setup and hold windows.

摘要翻译： 一种形成集成电路的方法包括提供集成电路的第一设计; 分析第一设计以识别具有建立/保持违规的第一触发器和没有建立/保持违规的第二触发器; 以及用与第一触发器基本相同的单元延迟的第三触发器替换第一触发器，以形成集成电路的第二设计。 第一个触发器和第三个触发器具有不同的设置和保持窗口。

公开(公告)号：US06453443B1

公开(公告)日：2002-09-17

申请号：US09835028

申请日：2001-04-16

申请人： Pi-Cheng Chen ,  Wen-Hao Chen ,  Ming-Chyuan Chen ,  Hsien-Te Chen

发明人： Pi-Cheng Chen ,  Wen-Hao Chen ,  Ming-Chyuan Chen ,  Hsien-Te Chen

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.

摘要翻译： 在本发明中，描述了一种方法来产生包括电压变化对延迟的影响的整个芯片定时验证。 这通过创建网表，定义单元输入和输出（I / O）延迟路径以及计算由电源电压差异引起的差异定时来完成。 通过增加由所有电源引脚引起的延迟更改来计算增量I / O路径延迟。 在不考虑电压降的情况下生成整个芯片定时，然后使用增量路径延迟进行修改。 经修改的全芯片定时数据文件与传统的定时验证工具一起使用，以执行整个芯片单元级定时验证。

公开(公告)号：US08726208B2

公开(公告)日：2014-05-13

申请号：US13186241

申请日：2011-07-19

申请人： Wen-Hao Chen ,  Zhe-Wei Jiang ,  Chung-Min Fu

发明人： Wen-Hao Chen ,  Zhe-Wei Jiang ,  Chung-Min Fu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

摘要翻译： 一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。 布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的各自的布局改变。

公开(公告)号：US20130091476A1

公开(公告)日：2013-04-11

申请号：US13269757

申请日：2011-10-10

申请人： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

发明人： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

摘要翻译： 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

公开(公告)号：US08856696B2

公开(公告)日：2014-10-07

申请号：US13354707

申请日：2012-01-20

申请人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

发明人： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5077

摘要： Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

摘要翻译： 公开了改进利用多重图案化技术（MPT）的集成电路（IC）设计的方法。 所述方法包括配置集成电路的第一布局，其具有至少一层具有通过至少两个掩模的制造而形成的特征的层。 该至少一层包括多个活动单元和多个备用单元。 第二布局被配置为重新路由备用单元和活动单元，其中重新路由使用多个备用单元的至少一部分。 比所有至少两个掩模更少，以配置第二个布局。