公开(公告)号：US06943585B2

公开(公告)日：2005-09-13

申请号：US10694966

申请日：2003-10-28

Applicant: Jae Jin Lee ,  Kang Seol Lee

Inventor： Jae Jin Lee ,  Kang Seol Lee

IPC: H03K19/018 ,  G11C7/10 ,  H03K19/00 ,  H03K19/0948

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C2207/2227 ,  H03K19/0016

Abstract: Disclosed is an input apparatus used in a SSTL interface, which comprises a differential buffer for comparing an external input signal with a reference potential inputted from an external, and a CMOS buffer for buffering the external input signal. In the input apparatus, the CMOS buffer operates when a command signal or an address signal is not inputted from an external, and when a predetermined operation such as a refresh operation is performed, thereby reducing the power consumption in a standby mode. Further, in order to prevent the input apparatus from abnormally operating when the reference potential is not maintained in the normal operation range, a reference potential level detecting circuit is further included in the input apparatus, so that the CMOS buffer operates when the reference potential deviates from a predetermined normal operation range. Furthermore, in order to enable an input buffer to operate as the CMOS when an input signal fully swings, a circuit for detecting a potential of an input signal inputted from an external is further included in the input apparatus.

Abstract translation: 公开了一种在SSTL接口中使用的输入装置，其包括用于将外部输入信号与从外部输入的参考电位进行比较的差分缓冲器和用于缓冲外部输入信号的CMOS缓冲器。 在输入装置中，当没有从外部输入命令信号或地址信号时，并且当执行诸如刷新操作的预定操作时，CMOS缓冲器操作，从而降低待机模式下的功耗。 此外，为了防止输入装置在基准电位不保持在正常工作范围时异常工作，在输入装置中还包括基准电位电平检测电路，使得CMOS缓冲器在参考电位偏移 从预定的正常操作范围。 此外，为了使输入缓冲器在输入信号完全摆动时作为CMOS工作，在输入装置中还包括用于检测从外部输入的输入信号的电位的电路。

公开(公告)号：US20050105378A1

公开(公告)日：2005-05-19

申请号：US10882454

申请日：2004-06-30

Applicant: Kang-Seol Lee

Inventor： Kang-Seol Lee

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/00

CPC classification number: G11C5/14

Abstract: A delay locked loop (DLL) power supply circuit for use in a semiconductor memory device, including: a DLL power supplier for supplying a DLL power supply voltage to a DLL in response to a reference voltage and a clock enable exit pulse signal; and a pulse signal generator for generating the clock enable exit pulse signal in response to a clock enable signal.

Abstract translation: 一种用于半导体存储器件的延迟锁定环路（DLL）电源电路，包括：DLL电源，用于响应于参考电压和时钟使能输出脉冲信号向DLL提供DLL电源电压; 以及脉冲信号发生器，用于响应于时钟使能信号产生时钟使能输出脉冲信号。

公开(公告)号：US06721211B2

公开(公告)日：2004-04-13

申请号：US10246083

申请日：2002-09-18

Applicant: Jae Jin Lee ,  Kang Seol Lee

Inventor： Jae Jin Lee ,  Kang Seol Lee

IPC: G11C700

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C11/4074 ,  G11C11/4096 ,  H02M3/07 ,  H02M2003/072

Abstract: A voltage generator for a semiconductor memory device that improves the drivability of an output driver by controlling a gate of the output driver to vary between an internal power supply voltage and a ground voltage, is disclosed. The voltage generator includes an output voltage controller to generate a pull-up signal for controlling a pull-up operation and a pull-down signal for controlling a pull-down operation, the pull-up signal having a level substantially equivalent to an internal power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, and having a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage. The voltage generator further includes an output driver to generate a stable cell plate voltage in response to the pull-up signal and the pull-down signal.

Abstract translation: 公开了一种用于半导体存储器件的电压发生器，其通过控制输出驱动器的栅极在内部电源电压和接地电压之间变化来提高输出驱动器的驱动能力。 电压发生器包括输出电压控制器以产生用于控制上拉操作的上拉信号和用于控制下拉操作的下拉信号，所述上拉信号的电平基本上等于内部功率 如果单元板电压高于单元板参考电压，并且如果单元板电压低于单元板参考电压，则具有低于单元板电压的电平的电源电压。 电压发生器还包括输出驱动器，以响应于上拉信号和下拉信号产生稳定的单元板电压。

公开(公告)号：US08970236B2

公开(公告)日：2015-03-03

申请号：US13154680

申请日：2011-06-07

Applicant: kang-Seol Lee ,  Seok-Cheol Yoon

Inventor： kang-Seol Lee ,  Seok-Cheol Yoon

IPC: G01R31/00 ,  G01R31/02 ,  G05F1/46 ,  G11C5/14 ,  G11C29/06 ,  G11C29/12

CPC classification number: G05F1/465 ,  G11C5/147 ,  G11C29/06 ,  G11C29/12005

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract translation: 内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。 内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。 因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。 结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

公开(公告)号：US08687443B2

公开(公告)日：2014-04-01

申请号：US13171747

申请日：2011-06-29

Applicant: Sang Hoon Shin ,  Kang Seol Lee

Inventor： Sang Hoon Shin ,  Kang Seol Lee

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/26 ,  G11C7/10 ,  G11C7/1006 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.

Abstract translation: 公开了半导体装置的各种实施例。 在一个示例性实施例中，半导体装置可以包括存储器块芯片和信号输入/输出芯片。 存储器块芯片被配置为根据规格控制数据访问大小。 信号输入/输出芯片被配置为将输入数据从外部设备发送到存储器块芯片，或者将输出数据从存储器块芯片发送到外部设备，并通过有选择地启用时钟相位控制来处理输入数据或输出数据 单元和信号处理单元。

公开(公告)号：US20120243355A1

公开(公告)日：2012-09-27

申请号：US13171747

申请日：2011-06-29

Applicant: Sang Hoon SHIN ,  Kang Seol Lee

Inventor： Sang Hoon SHIN ,  Kang Seol Lee

IPC: G11C29/00 ,  G11C8/00 ,  G11C8/10

CPC classification number: G11C29/26 ,  G11C7/10 ,  G11C7/1006 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.

Abstract translation: 公开了半导体装置的各种实施例。 在一个示例性实施例中，半导体装置可以包括存储器块芯片和信号输入/输出芯片。 存储器块芯片被配置为根据规格控制数据访问大小。 信号输入/输出芯片被配置为将输入数据从外部设备发送到存储器块芯片，或者将输出数据从存储器块芯片发送到外部设备，并通过有选择地启用时钟相位控制来处理输入数据或输出数据 单元和信号处理单元。

公开(公告)号：US08111569B2

公开(公告)日：2012-02-07

申请号：US12644979

申请日：2009-12-22

Applicant: Kang Seol Lee ,  Eun Souk Lee

Inventor： Kang Seol Lee ,  Eun Souk Lee

IPC: G11C7/00

CPC classification number: H01L27/092 ,  H01L27/0207

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract translation: 锁存结构包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管，接收第一反相器的输出信号，并将输入信号输出到 第一台逆变器。 相同类型的第一和第二晶体管的源极连接到公共直线源极线。

公开(公告)号：US20110234288A1

公开(公告)日：2011-09-29

申请号：US13154680

申请日：2011-06-07

Applicant: Kang-Seol LEE ,  Seok-Cheol Yoon

Inventor： Kang-Seol LEE ,  Seok-Cheol Yoon

IPC: H03L5/00

CPC classification number: G05F1/465 ,  G11C5/147 ,  G11C29/06 ,  G11C29/12005

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract translation: 内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。 内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。 因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。 结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

公开(公告)号：US08008943B2

公开(公告)日：2011-08-30

申请号：US12958634

申请日：2010-12-02

Applicant: Tae-Sik Yun ,  Kang-Seol Lee

Inventor： Tae-Sik Yun ,  Kang-Seol Lee

IPC: H03K19/00

CPC classification number: G01R31/318511 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48

Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.

Abstract translation: 半导体器件包括多个被配置为接收多个外部信号的焊盘，内部电路被配置为响应于通过多个焊盘之一输入的外部信号之一执行预定的内部操作，以及信号传输 被配置为接收外部信号的单元，在正常模式期间将外部信号输出到内部电路的输出信号，并且在测试模式中输出固定信号，而不管外部信号对内部电路的变化。

公开(公告)号：US07969795B2

公开(公告)日：2011-06-28

申请号：US11819786

申请日：2007-06-29

Applicant: Kang-Seol Lee

Inventor： Kang-Seol Lee

IPC: G11C5/14 ,  G11C7/04

CPC classification number: G11C5/145 ,  G11C7/04 ,  G11C11/4074

Abstract: A negative voltage generator of a semiconductor memory device includes: a flag signal generation unit for receiving a temperature information code from an On Die Thermal Sensor (ODTS) to output a plurality of flag signals containing temperature information of the semiconductor memory device; and a negative voltage detection unit for detecting a negative voltage to output a detection signal for determining whether to pump a negative voltage, wherein a detection level of the negative voltage is changed according to the flag signals.

Abstract translation: 半导体存储器件的负电压发生器包括：标志信号生成单元，用于从On Die热敏传感器（ODTS）接收温度信息代码，以输出包含半导体存储器件的温度信息的多个标志信号; 以及负电压检测单元，用于检测负电压以输出用于确定是否泵送负电压的检测信号，其中根据标志信号改变负电压的检测电平。