APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING A HYBRID VOLTAGE REGULATOR
    41.
    发明申请
    APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING A HYBRID VOLTAGE REGULATOR 审中-公开
    用于提供混合电压调节器的装置,系统和方法

    公开(公告)号:US20140306648A1

    公开(公告)日:2014-10-16

    申请号:US14250990

    申请日:2014-04-11

    Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

    Abstract translation: 本公开显示了混合调节器拓扑,其可以更容易地集成,并且即使使用小电感器也可以在宽输出和输入电压范围内保持高效率。 混合调节器拓扑可以包括两种类型的调节器:一个飞行开关电感调节器和一个降压调节器,将输入电压分压为输入电压的M / N分数。 所公开的混合调节器拓扑的实施例可以通过限制飞越开关 - 电感器调节器中的开关两端的电压摆幅来减小飞行开关电感器调节器的电容损耗。 所公开的混合调节器拓扑的实施例可以通过以高开关频率和通过电感器的少量电流流动操作飞行开关电感器调节器来减小飞行开关电感器调节器的电感器电阻损耗。

    DC VOLTAGE CONVERTERS
    42.
    发明公开

    公开(公告)号:US20240146194A1

    公开(公告)日:2024-05-02

    申请号:US18548401

    申请日:2022-03-24

    Inventor: Hans MEYVAERT

    CPC classification number: H02M3/158 G05F1/613 H02J1/082 H02M1/009

    Abstract: This application relates to methods and apparatus for DC voltage conversion. A DC converter (100) is described, with a charge pump circuit comprising a plurality of charge pump stages (1401, 1402-2, 1402-2) each charge pump stage comprising connections for respective first and second capacitors for that stage (C1A, C1B; C2A, C2B; C3A, C3B). The charge pump also has a switch network, wherein the switch network comprises, between each successive stage, four switching paths (S7AA, S7AB, S7Ba, S7BB; S6AA, S6AB, S6Ba, S6BB) for separately connecting a respective first electrode of each of the first and second capacitors of one stage to a first electrode either of the first and second capacitors of the preceding stage, so that the relevant capacitor of the one stage can be charged by the relevant capacitor of the preceding stage.

    CIRCUITS FOR SWITCHED CAPACITOR VOLTAGE CONVERTERS

    公开(公告)号:US20210305895A1

    公开(公告)日:2021-09-30

    申请号:US17213268

    申请日:2021-03-26

    Inventor: Hans Meyvaert

    Abstract: A circuit comprising: a first switch having: first side (FS) connected to first capacitor's second side (1C2S); and second side (SS) connected to reference node (RN); a second switch having: FS connected to second voltage node (2VN); and SS connected to 1C2S; a third switch having: FS connected to the first capacitor's first side (1C1S); and SS connected to 2VN; a fourth switch having: FS connected to a third voltage node (3VN); and SS connected to 1C1S; a fifth switch having: FS connected to second capacitor's second side (2C2S); and SS connected to RN; a sixth switch having: FS connected to 3VN; and SS connected to 2C2S; a seventh switch having: FS connected to the second capacitor's first side (2C1S); and SS connected to 3VN; and an eighth switch having: FS connected to first voltage node; and SS connected to 2C1S.

    Circuits and methods for slew rate control of switched capacitor regulators

    公开(公告)号:US10715035B2

    公开(公告)日:2020-07-14

    申请号:US15903974

    申请日:2018-02-23

    Abstract: Circuits comprising: a first capacitor(C1); a first switch(S1) having a first side coupled to a VIN and a second side coupled to a first side of C1; a second switch(S2) having a first side coupled to the second side of S1; a third switch(S3) having a first side coupled to a second side of S2 and a second side coupled to a second side of C1; a fourth switch(S4) having a first side coupled to a second side of S3 and a second side coupled to a VSUPPLY, wherein: in a first state, S1 and S3 are off, and S2 and S4 are on; in a second state, S1 and S3 are on, and S2 and S4 are off; and at least one of a control of S1, a control of S2, a control of S3, and a control of S4 is coupled to a time-varying-slew-rate signal.

    CIRCUITS AND METHODS FOR SLEW RATE CONTROL OF SWITCHED CAPACITOR REGULATORS

    公开(公告)号:US20190265743A1

    公开(公告)日:2019-08-29

    申请号:US15903974

    申请日:2018-02-23

    Abstract: Circuits comprising: a first capacitor(C1); a first switch(S1) having a first side coupled to a VIN and a second side coupled to a first side of C1; a second switch(S2) having a first side coupled to the second side of S1; a third switch(S3) having a first side coupled to a second side of S2 and a second side coupled to a second side of C1; a fourth switch(S4) having a first side coupled to a second side of S3 and a second side coupled to a VSUPPLY, wherein: in a first state, S1 and S3 are off, and S2 and S4 are on; in a second state, S1 and S3 are on, and S2 and S4 are off; and at least one of a control of S1, a control of S2, a control of S3, and a control of S4 is coupled to a time-varying-slew-rate signal.

    CIRCUITS FOR THREE-LEVEL BUCK REGULATORS
    47.
    发明申请

    公开(公告)号:US20190214905A1

    公开(公告)日:2019-07-11

    申请号:US15868496

    申请日:2018-01-11

    CPC classification number: H02M3/158 H02M1/32

    Abstract: An inductor; a first switch having a first side connected to a first voltage source (VS1); a second switch having a first side connected to a second side of the first switch (2SS1), and a second side connected to a first side of the inductor (1SI); a third switch having a first side connected to the 1SI; a fourth switch having a first side connected to a second side of the third switch (2SS3), and a second side connected to a second voltage source (VS2); a fifth switch having a first side connected to the 1SI, and a second side connected to the VS1 and/or the VS2; a first capacitor having a first side connected to the 2SS1, and a second side connected to the 2SS3; and a second capacitor having a first side connected to a second side of the inductor, and a second side connected to the VS2.

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