公开(公告)号：US06791865B2

公开(公告)日：2004-09-14

申请号：US10232363

申请日：2002-09-03

Applicant: Lung T. Tran ,  Manoj K. Bhattacharyya

Inventor： Lung T. Tran ,  Manoj K. Bhattacharyya

IPC: G11C1100

CPC classification number: G11C29/028 ,  G11C11/15 ,  G11C11/16 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.

公开(公告)号：US06778421B2

公开(公告)日：2004-08-17

申请号：US10098903

申请日：2002-03-14

Applicant: Lung T. Tran

Inventor： Lung T. Tran

IPC: G11C1706

CPC classification number: G11C11/16 ,  H01L27/224

Abstract: A magnetic random access memory (MRAM) device having parallel memory planes is disclosed. Each memory plane includes a first magneto-resistive cross point plane of memory cells, a second magneto-resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a first plurality of bit lines, each of the first plurality of bit lines coupling one or more cells from the first plane to at least one other memory cell in the first plane, a second plurality of bit lines, each of the second plurality of bit lines coupling one or more cells from the second plane to at least one other memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.

Abstract translation: 公开了一种具有并行存储器平面的磁性随机存取存储器（MRAM）器件。 每个存储器平面包括存储器单元的第一磁阻交叉点平面，存储器单元的第二磁阻交叉点平面，在存储器单元的第一和第二平面之间共享的多个导电字线，第一多个位 所述第一多个位线中的每一个将所述第一平面中的一个或多个单元耦合到所述第一平面中的至少一个其它存储单元，所述第二多个位线，所述第二多个位线中的每一个耦合一个或多个 单元从第二平面到第二平面中的至少一个其它存储单元，以及多个单向元件。 此外，一个单向元件将第一存储器单元从第一平面耦合到所选择的字线，并且第一导电方向上的选定位线和第二单向元件将第二单元从第二平面耦合到所选择的字线并选择 位线在第二导电方向上。 该装置还提供从第一平面中的存储器单元形成到共享相同位线的第二平面中的存储器单元的单向导电路径。

公开(公告)号：US06577529B1

公开(公告)日：2003-06-10

申请号：US10235011

申请日：2002-09-03

Applicant: Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

Inventor： Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

IPC: G11C1100

CPC classification number: G11C11/15 ,  G11C11/5607 ,  G11C2213/71

Abstract: A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.

Abstract translation: 存储单元包括用铁磁材料包覆的导体; 在包层导体的相对侧上的第一和第二间隔层; 第一间隔层上的第一数据层; 以及第二间隔层上的第二数据层。

公开(公告)号：US06538917B1

公开(公告)日：2003-03-25

申请号：US09963851

申请日：2001-09-25

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C1115

CPC classification number: G11C11/16

Abstract: A magneto-resistive device includes data and reference layers having different coercivities. Each layer has a magnetization that can be oriented in either of two directions. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.

Abstract translation: 磁阻装置包括具有不同矫顽力的数据和参考层。 每个层具有可以在两个方向中的任一方向上定向的磁化。 可以通过将参考层的磁化临时设置为已知取向来读取存储器件，并且确定器件的电阻状态。

公开(公告)号：US06434060B1

公开(公告)日：2002-08-13

申请号：US09917882

申请日：2001-07-31

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C700

CPC classification number: G11C16/3486 ,  G11C17/16 ,  G11C17/18

Abstract: A method and circuit write a memory cell. The method applies a pulse to a write line connected to the memory cell. The duration of the pulse is not predetermined. The method compares a value on the input side of the cell to a reference value. The method discontinues the pulse on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. The circuit comprises a pulse generator and a comparator. The pulse generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the write line, whereby the pulse is disabled or enabled on the write line depending upon comparator output. A complete memory system comprises an array of memory cells, a write line, and a pulse generator and comparator as described above.

Abstract translation: 一种方法和电路写入一个存储单元。 该方法向连接到存储单元的写入线施加脉冲。 脉冲的持续时间不是预定的。 该方法将单元格输入端的值与参考值进行比较。 该方法响应于比较步骤中止写入线上的脉冲，优选地，如果写入线上的值超过参考值。 电路包括脉冲发生器和比较器。 脉冲发生器具有输出和使能输入。 输出连接到连接到存储单元的写入线。 输出，当使能时，会携带一个脉冲。 比较器有两个输入和一个输出。 其中一个输入连接到写入线。 另一个输入连接到引用。 输出连接到写入线，根据比较器输出，脉冲在写入线上被禁止或使能。 完整的存储器系统包括如上所述的存储器单元阵列，写入线以及脉冲发生器和比较器。

公开(公告)号：US06434048B1

公开(公告)日：2002-08-13

申请号：US09908901

申请日：2001-07-20

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C700

CPC classification number: G11C7/1084 ,  G11C7/1006 ,  G11C7/1078

Abstract: A method and circuit write a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on the input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse train. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output. Optionally, the circuit further comprises a counter that counts pulses and disables the pulse train generator after a predetermined maximum number of pulses. A complete memory system comprises an array of memory cells, a write line, and a pulse train generator and comparator as described above.

Abstract translation: 一种方法和电路写入一个存储单元。 该方法将脉冲串应用于连接到存储单元的写入线。 脉冲串中的脉冲数不是预定的。 该方法将小区的输入侧的值与参考值进行比较，其中存储单元的输入侧提供写入操作完成的指示。 该方法响应于比较步骤中止写入线上的脉冲序列，优选地，如果写入线上的值超过参考值。 优选地，脉冲的宽度较短，而且幅度较大。 该方法可以可选地计数脉冲串中的脉冲数，并且如果脉冲数超过预定最大值，则在写入线上中止脉冲序列和/或将单元声明为不可用。 电路包括脉冲串发生器和比较器。 脉冲串发生器具有输出和使能输入。 输出连接到连接到存储单元的写入线。 输出，当使能时，携带脉冲串。 比较器有两个输入和一个输出。 其中一个输入连接到写入线。 另一个输入连接到引用。 输出连接到脉冲串发生器的使能输入端，根据比较器输出，脉冲串发生器被禁止或使能。 可选地，电路还包括计数器，其计数脉冲并且在预定的最大脉冲数之后禁用脉冲序列发生器。 完整的存储器系统包括如上所述的存储器单元阵列，写入线以及脉冲序列发生器和比较器。

公开(公告)号：US06385111B2

公开(公告)日：2002-05-07

申请号：US09809707

申请日：2001-03-14

Applicant: Lung T. Tran ,  Kenneth J. Eldredge

Inventor： Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C702

CPC classification number: G11C11/16 ,  G11C7/14 ,  G11C27/02

Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract translation: 磁性随机存取存储器（“MRAM”）装置包括一组存储单元。 该器件产生可用于确定阵列中每个存储单元的电阻状态的参考信号，尽管由于制造公差和其他因素（例如阵列上的温度梯度，电磁干扰和衰老）导致的电阻变化。

公开(公告)号：US06256224B1

公开(公告)日：2001-07-03

申请号：US09564713

申请日：2000-05-03

Applicant: Frederick A Perner ,  Kenneth J Eldredge ,  Lung T Tran

Inventor： Frederick A Perner ,  Kenneth J Eldredge ,  Lung T Tran

IPC: G11C1115

CPC classification number: G11C11/16 ,  G11C11/15

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract translation: 用于磁随机存取存储器（“MRAM”）器件的大量存储器单元的写入电路。 写入电路可以在不超过存储器单元的击穿极限的情况下向所选择的字和位线提供可控的双向写入电流。 此外，写入电路可以随着时间推移写入电流以减少峰值电流。

公开(公告)号：US5930087A

公开(公告)日：1999-07-27

申请号：US974420

申请日：1997-11-20

Applicant: James A. Brug ,  Manoj K. Bhattacharyya ,  Lung T. Tran ,  Thomas C. Anthony

Inventor： James A. Brug ,  Manoj K. Bhattacharyya ,  Lung T. Tran ,  Thomas C. Anthony

IPC: G11B5/11 ,  G11B5/33 ,  G11B5/39 ,  G11B5/40 ,  G11B19/04 ,  H01F10/32

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11B5/33 ,  G11B5/332 ,  G11B5/3903 ,  G11B5/3909 ,  G11B5/3919 ,  G11B5/40 ,  H01F10/3268 ,  G11B19/04 ,  G11B5/11 ,  G11B5/3912 ,  G11B5/3967

Abstract: A robust recording head with a spin tunneling sensing element separated from an interface between the recording head and a recording media so as not to be affected by collisions and other ill effects at the interface between the recording head and the recording media. The spin tunneling sensing element includes a pair of magnetic elements wherein one of the magnetic elements functions as a flux guide that conducts magnetic flux emanating from the recording media away from the interface to an active area of the spin tunneling sensing element.

Abstract translation: 一种坚固的记录头，其具有与记录头和记录介质之间的接口分开的自旋隧道感测元件，以便不受记录头和记录介质之间的界面处的碰撞和其它不良影响的影响。 自旋隧道感测元件包括一对磁性元件，其中一个磁性元件用作将从记录介质发出的磁通远离界面移动到自旋隧道感应元件的有效区域的磁通引导件。

公开(公告)号：US4878140A

公开(公告)日：1989-10-31

申请号：US209651

申请日：1988-06-21

Applicant: Hardayal S. Gill ,  Victor W. Hesterman ,  Giora J. Tarnopolsky ,  Lung T. Tran

Inventor： Hardayal S. Gill ,  Victor W. Hesterman ,  Giora J. Tarnopolsky ,  Lung T. Tran

IPC: G11B5/00 ,  G11B5/02 ,  G11B5/127 ,  G11B5/39 ,  G11B19/04

CPC classification number: G11B5/3954 ,  G11B19/04 ,  G11B5/02 ,  G11B5/1278 ,  G11B5/39 ,  G11B5/3903 ,  G11B2005/0029

Abstract: A sensor for reading perpendicularly recorded media includes dual magneto-resistive elements. Directionally opposed currents through respective elements each serve both sensing and bias functions. A detector differentially detects changes in the resistance of the stripes so as to presume common mode noise rejection when reading perpendicular recording media. In addition, the opposing currents offset each other's interaction with the soft magnetic underlayer of the media, which interaction could otherwise perturb the information stored on the media. Provision is made for switching the relative direction of current flow to provide for reading longitudinally recorded media.