公开(公告)号：US06873544B2

公开(公告)日：2005-03-29

申请号：US10696826

申请日：2003-10-30

Applicant: Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

Inventor： Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC classification number: G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C27/02 ,  G11C2013/0057

Abstract: A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.

Abstract translation: 一种包括电阻式存储单元阵列的数据存储装置。 电阻存储单元可以包括磁性隧道结（MTJ）和薄膜二极管。 该装置可以包括电连接到阵列的电路，并且还能够监测流过所选择的存储器单元的信号电流。 一旦已经监视了信号电流，电路就可以将信号电流与平均参考电流进行比较，以确定所选择的存储单元处于第一电阻状态和第二电阻状态。另外，一种操作方法 数据存储设备。

公开(公告)号：US06757188B2

公开(公告)日：2004-06-29

申请号：US10151915

申请日：2002-05-22

Applicant: Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

Inventor： Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C1100

CPC classification number: G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C27/02 ,  G11C2013/0057

Abstract: A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.

公开(公告)号：US06317376B1

公开(公告)日：2001-11-13

申请号：US09598671

申请日：2000-06-20

Applicant: Lung T. Tran ,  Kenneth J. Eldredge

Inventor： Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C702

CPC classification number: G11C11/16 ,  G11C7/14 ,  G11C27/02

Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract translation: 磁性随机存取存储器（“MRAM”）装置包括一组存储单元。 该器件产生可用于确定阵列中每个存储单元的电阻状态的参考信号，尽管由于制造公差和其他因素（例如阵列上的温度梯度，电磁干扰和衰老）导致的电阻变化。

公开(公告)号：US06262625B1

公开(公告)日：2001-07-17

申请号：US09430238

申请日：1999-10-29

Applicant: Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung T. Tran

Inventor： Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung T. Tran

IPC: G01R1900

CPC classification number: B82Y10/00 ,  G11C11/15 ,  H03F1/304 ,  H03F3/45771 ,  H03F2203/45048 ,  H03F2203/45291 ,  H03F2203/45342 ,  H03F2203/45624 ,  H03F2203/45726

Abstract: An operational amplifier includes transistors for providing a controlled current path. At least one of the transistors is in an isolated well in a substrate. Offset of the operational amplifier is corrected by applying a back gate bias voltage to at least one isolated well and changing impedance of the transistors. The proper back gate bias voltage and transistor impedance are determined by incrementally adjusting the back gate bias voltage and then incrementally adjusting the transistor impedance. Calibration values are stored in register memory. Such calibration may be performed by an auto offset calibration process.

Abstract translation: 运算放大器包括用于提供受控电流路径的晶体管。 至少一个晶体管处于衬底中的隔离阱中。 通过对至少一个隔离阱施加背栅偏置电压并改变晶体管的阻抗来校正运算放大器的偏移。 正确的背栅偏置电压和晶体管阻抗通过逐步调整背栅偏置电压然后逐渐调整晶体管阻抗来确定。 校准值存储在寄存器存储器中。 这种校准可以通过自动偏移校准过程来执行。

公开(公告)号：US06188615B1

公开(公告)日：2001-02-13

申请号：US09430611

申请日：1999-10-29

Applicant: Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung T. Tran

Inventor： Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung T. Tran

IPC: G11C1604

CPC classification number: G11C11/15 ,  G11C7/067 ,  G11C16/32

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).

Abstract translation: 通过包括直接注入电荷放大器，积分器电容器和数字读出放大器的读取电路来检测磁性随机存取存储器（“MRAM”）器件中的所选存储单元的电阻。 直接注入电荷放大器向积分器电容器提供电流，同时在MRAM器件中的未选择的存储单元上保持等电位电压。 由于直接注入电荷放大器对所选择的存储单元施加固定电压，所以读出放大器测量积分器上信号的积分时间。 信号积分时间表示存储单元MRAM电阻是处于第一状态（R）还是第二状态（R + DELTAR）。

公开(公告)号：US06385111B2

公开(公告)日：2002-05-07

申请号：US09809707

申请日：2001-03-14

Applicant: Lung T. Tran ,  Kenneth J. Eldredge

Inventor： Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C702

CPC classification number: G11C11/16 ,  G11C7/14 ,  G11C27/02

Abstract: A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.

Abstract translation: 磁性随机存取存储器（“MRAM”）装置包括一组存储单元。 该器件产生可用于确定阵列中每个存储单元的电阻状态的参考信号，尽管由于制造公差和其他因素（例如阵列上的温度梯度，电磁干扰和衰老）导致的电阻变化。

公开(公告)号：US07376004B2

公开(公告)日：2008-05-20

申请号：US10661448

申请日：2003-09-11

Applicant: James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

Inventor： James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C11/00 ,  G11C11/14

CPC classification number: G11C11/16

Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.

Abstract translation: 用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。 一些实施例使用用于这种电隔离的串联连接的二极管。 只有选定的一个存储器单元将在相应的位和字线之间传导电流。 读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。 在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。 在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。

公开(公告)号：US20120278684A1

公开(公告)日：2012-11-01

申请号：US13543191

申请日：2012-07-06

Applicant: Kenneth J. Eldredge ,  Stephen P. Van Aken

Inventor： Kenneth J. Eldredge ,  Stephen P. Van Aken

IPC: G06F12/06 ,  H03M13/05 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract translation: 一种使用闪存设备存储和检索数据的方法和系统。 一个示例系统包括闪存配置内的设备。 闪速存储器配置包括多个存储器单元，其中每个存储器单元具有用于实现数字存储器的电荷存储容量。 该装置包括配置成在写入操作和读取操作中访问每个存储器单元的处理装置。 该装置还包括用于指示处理器施加用于为每个存储单元定义多个数据值的目标电荷电平的指令集。 目标电荷电平可编程地相对于电荷存储容量移动。

公开(公告)号：US07877564B2

公开(公告)日：2011-01-25

申请号：US11834565

申请日：2007-08-06

Applicant: Kenneth J. Eldredge ,  Stephen P. Van Aken

Inventor： Kenneth J. Eldredge ,  Stephen P. Van Aken

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract translation: 一种使用闪存设备存储和检索数据的方法和系统。 一个示例系统包括闪存配置内的设备。 闪速存储器配置包括多个存储器单元，其中每个存储器单元具有用于实现数字存储器的电荷存储容量。 该装置包括配置成在写入操作和读取操作中访问每个存储器单元的处理装置。 该装置还包括用于指示处理器施加用于为每个存储器单元定义多个数据值的目标充电水平的指令集。 目标电荷电平可编程地相对于电荷存储容量移动。

公开(公告)号：US07310298B2

公开(公告)日：2007-12-18

申请号：US10849752

申请日：2004-05-20

Applicant: Richard L Hilton ,  Kenneth J. Eldredge

Inventor： Richard L Hilton ,  Kenneth J. Eldredge

IPC: G11B7/00

CPC classification number: G11B9/1472 ,  B82Y10/00

Abstract: A storage device includes a probe and a storage medium having a plurality of storage cells. The probe is able to form a first structure and a second structure in the storage medium, where a first storage cell containing a transition between the first structure and a second structure contains a data bit having a first state, and where a second storage cell not including a transition between the first structure and the second structure contains a data bit having a second state.

Abstract translation: 存储装置包括探针和具有多个存储单元的存储介质。 探针能够在存储介质中形成第一结构和第二结构，其中包含第一结构和第二结构之间的转变的第一存储单元包含具有第一状态的数据位，并且其中第二存储单元不 包括第一结构和第二结构之间的转换包含具有第二状态的数据位。