公开(公告)号：US07605603B1

公开(公告)日：2009-10-20

申请号：US12040100

申请日：2008-02-29

Applicant: Michael D. Hutton ,  Andy L. Lee

Inventor： Michael D. Hutton ,  Andy L. Lee

IPC: H03K19/173

CPC classification number: H03K19/17748 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

公开(公告)号：US07545196B1

公开(公告)日：2009-06-09

申请号：US11550132

申请日：2006-10-17

Applicant: Michael D. Hutton ,  Kumara Tharmalingam ,  Yi-Wen Lin ,  David Neto

Inventor： Michael D. Hutton ,  Kumara Tharmalingam ,  Yi-Wen Lin ,  David Neto

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: Clocks are distributed efficiently to regions of a specialized processing block in a PLD. Multiple clocks are selected from a larger universe of clocks and distributed to the specialized processing block, but the choices of clocks at the individual functional regions, or stages of functional regions, are less than fully flexible. In some cases, an entire region may use one clock. In another case, portions of a stage within a region that previously had been able to select individual clocks must use one clock for the entire stage. In another case, only a subset of the selected clocks is available for a particular region, but that subset is flexibly distributable within the region. In another case, a clock may be selectable for each stage of each functional region directly from the larger universe of available clocks, avoiding the need for circuitry to select the multiple clocks from the larger universe.

Abstract translation: 时钟有效地分布在PLD中的专门处理块的区域。 多个时钟选自较大的时钟范围，并分配到专门的处理块，但是各个功能区或功能区的阶段的时钟选择小于完全灵活。 在某些情况下，整个区域可能使用一个时钟。 在另一种情况下，先前已经能够选择各个时钟的区域中的一部分的部分必须在整个阶段使用一个时钟。 在另一种情况下，只有所选择的时钟的子集可用于特定区域，但该子集可在该区域内灵活分配。 在另一种情况下，可以直接从较大的可用时钟范围为每个功能区域的每一级选择一个时钟，避免了从较大宇宙中选择多个时钟的电路的需要。

公开(公告)号：US07469394B1

公开(公告)日：2008-12-23

申请号：US11502320

申请日：2006-08-09

Applicant: Michael D. Hutton ,  Yan Lin

Inventor： Michael D. Hutton ,  Yan Lin

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F8/41

Abstract: Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of device, such as the mean and variance values of attributes. A compilation phase evaluates the suitability of a potential configuration of the device using a cost function. The cost function can be based on one or more independent criteria of the design, such wiring or routing costs, timing costs, and power consumption costs. The compilation phase can include clustering, placement, and routing of the design. One or more of the cost function criteria can include statistical attributes of the device. The compilation software can use statistical attributes of the device to predict device yields for a design. The compilation software can also predict device yields of a design using devices of different speed bin classifications.

Abstract translation: 设计编译软件使用统计分析技术来解释设备属性的变化。 汇编阶段确定设备边缘和其他元素的统计属性，如属性的均值和方差值。 编译阶段使用成本函数来评估设备的潜在配置的适用性。 成本函数可以基于设计的一个或多个独立标准，例如布线或布线成本，定时成本和功耗成本。 编译阶段可以包括设计的聚类，布局和布线。 一个或多个成本函数标准可以包括设备的统计属性。 编译软件可以使用设备的统计属性来预测设计的设备收益。 编译软件还可以使用不同速度仓分类的设备来预测设计的产量。

公开(公告)号：US07420390B1

公开(公告)日：2008-09-02

申请号：US11328407

申请日：2006-01-09

Applicant: Michael D. Hutton ,  James G. Schleicher, II

Inventor： Michael D. Hutton ,  James G. Schleicher, II

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

Abstract: A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.

Abstract translation: 现场可编程门阵列包括多个可编程逻辑块以实现一个或多个逻辑功能。 现场可编程门阵列包括不与多个可编程逻辑块中的任何特定的一个相关联的多个独立寄存器。 多个独立寄存器可被编程为支持多个可编程逻辑块中的任何一个。

公开(公告)号：US07394287B1

公开(公告)日：2008-07-01

申请号：US11751392

申请日：2007-05-21

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/173

CPC classification number: H03K19/17728

Abstract: A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. In one embodiment, the logic cell further includes a first output register and a second output register and the set of outputs generated by the logic cell are partitioned among the first output register and the second output register. In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or “packing” by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals.

Abstract translation: 公开了具有逻辑单元的具有改进的逻辑，寄存器，算术，逻辑封装和定时功能和能力的基于CLB的PLD。 PLD的CLB被布置成阵列的行和列，并且通过多条互连线互连。 多个CLB中的每一个具有布置在第一列和第二列中的逻辑单元的第一切片和逻辑单元的第二切片。 在每列的每个逻辑单元之间提供第一和第二进位链。 逻辑单元中的至少一个包括用于在提供给一个逻辑单元的一组输入上植入逻辑功能的一个或多个查找表和被配置为接收进位信号并产生进位输出信号的算术逻辑电路 形成第一个进位链的一部分。 在一个实施例中，逻辑单元还包括第一输出寄存器和第二输出寄存器，并且逻辑单元产生的输出集合在第一输出寄存器和第二输出寄存器之间被分区。 在另一实施例中，寄存器之一的输出通过寄存器反馈连接被提供作为单元的查找表之一的输入。 在另一个实施例中，提供给第一和第二查找表的输入组是不同的，通过使每个单元能够在两组不同的输入集上执行逻辑功能，能够实现更高程度的逻辑效率或“打包”，如 反对只有同一组投入。 最后，在另一个实施例中，算术逻辑电路能够产生两个SUM输出信号。

公开(公告)号：US07368942B1

公开(公告)日：2008-05-06

申请号：US11351882

申请日：2006-02-09

Applicant: Michael D. Hutton ,  Bruce B. Pedersen ,  James G. Schleicher, II

Inventor： Michael D. Hutton ,  Bruce B. Pedersen ,  James G. Schleicher, II

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.

Abstract translation: 本发明一般来说涉及利用与可编程逻辑器件中的数字信号处理块相邻的逻辑组的现有输出来扩展数字信号处理块的功能。 来自逻辑组的输出被用作为数字信号处理块（例如，转换为功能特定块）提供附加输入的专用路由互连，使得信号处理块接收附加信号。 这些附加信号可以经由专用路由互连而被输入到信号处理块中，而不会显着增加硅区域昂贵的输入互连资源。

公开(公告)号：US07330052B2

公开(公告)日：2008-02-12

申请号：US11234538

申请日：2005-09-22

Applicant: Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

Inventor： Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

IPC: G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1737

Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

Abstract translation: 可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。 每个2-LUT包括四个存储元件。 每个存储器元件被配置为保持一个数据位。 可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。 当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。 当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。 另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集 一组六个输入。

公开(公告)号：US07093219B1

公开(公告)日：2006-08-15

申请号：US10718978

申请日：2003-11-20

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the graph is assigned a binary edge mask, each bit of which indicates whether it is reachable from a source or destination type relevant to user specified timing constraints. A timing analysis tool then performs multiple depth-first search operations to compute delays along time critical paths relevant to the user specified timing constraints. Because each edge contains an edge mask to indicate whether it connects to a particular source or destination point, the timing analysis tool does not analyze areas of the graph that do not lead to a relevant source or destination point. These techniques prevent the timing analysis tool from analyzing paths in the graph that are not relevant to the analysis of the time critical paths.

公开(公告)号：US06977520B1

公开(公告)日：2005-12-20

申请号：US10219085

申请日：2002-08-13

Applicant: Michael D. Hutton ,  Richard G. Cliff

Inventor： Michael D. Hutton ,  Richard G. Cliff

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1774 ,  H03K19/17792

Abstract: Programmable logic device interconnection resources include bus wires. A bus wire provides a programmable signal path across the programmable logic device from several logic device outputs to several other logic device inputs.Serializing circuitry multiplexes multiple device output signals and drives time-multiplexed data signals on the bus wires. Bus registers placed at the ends of bus wires register or buffer the data signals transmitted over the bus wires. The registered signals are passed on to deserializing circuitry for demultiplexing data signals to provide parallel device input signals. The bus registers, and the serializing/deserializing circuitry are clocked at a rate faster than the device system clock to schedule the use of the bus wires for transmission of multiple device input/output signals over the bus wires within a system clock cycle.

Abstract translation: 可编程逻辑器件互连资源包括母线。 总线线路将可编程逻辑器件的可编程信号路径从若干逻辑器件输出提供给其他几个逻辑器件输入。 串行化电路复用多个器件输出信号并在总线上驱动时间复用数据信号。 布置在总线末端的总线寄存器寄存或缓冲通过总线发送的数据信号。 注册的信号被传递到用于解复用数据信号的反序列化电路以提供并行设备输入信号。 总线寄存器和序列化/反序列化电路以比器件系统时钟速度更快的速度进行计时，以调度在系统时钟周期内通过总线传输多个器件输入/输出信号的总线线路。

公开(公告)号：US08860458B2

公开(公告)日：2014-10-14

申请号：US13555014

申请日：2012-07-20

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/173

CPC classification number: G06F17/5054 ,  H03K19/17744

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry. Computer-aided design tools may be used to identify registers in a design that should be used for register pipelining.

Abstract translation: 诸如可编程集成电路的集成电路可以包括可被配置为执行定制功能的可编程逻辑区域。 互连可用于在整个集成电路中路由信号。 可编程逻辑区域可以具有输入选择电路，用于选择并提供从互连到可编程逻辑区域的输入信号。 可编程逻辑区域可以包括用于处理输入信号的查找表电路和用于存储来自查找表电路的输出信号的寄存器。 可编程逻辑区域可以包括用于选择向可编程逻辑区域的输出电路提供哪些输出信号的输出选择电路。 可编程逻辑区域可以包括通过旁路输入和输出选择电路来提供从互连对寄存器的直接访问的旁路路径。 计算机辅助设计工具可用于识别应用于注册流水线的设计中的寄存器。