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1.发明申请FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 审中-公开具有集成应用的现场可编程阵列特殊集成电路布公开(公告)号：US20130009666A1
公开(公告)日：2013-01-10
申请号：US13613925
申请日：2012-09-13
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译： 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。
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2.发明授权Field programmable gate array with integrated application specific integrated circuit fabric 有权具有集成专用集成电路结构的现场可编程门阵列公开(公告)号：US08314636B2
公开(公告)日：2012-11-20
申请号：US12767696
申请日：2010-04-26
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译： 提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。
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3.发明授权Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device 有权用于在可编程逻辑器件中查询表输出的算术覆盖的装置和方法公开(公告)号：US07812633B1
公开(公告)日：2010-10-12
申请号：US11584308
申请日：2006-10-20
申请人： Andy L. Lee , David Lewis , Philip Pan , James G. Schleicher, II
发明人： Andy L. Lee , David Lewis , Philip Pan , James G. Schleicher, II
IPC分类号： H03K19/173 , H01L25/00
CPC分类号： H03K19/17728
摘要： A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.
摘要翻译： 具有具有N级查找表（LUT）的逻辑元件，用于执行非LUT逻辑功能的专用硬件的可编程逻辑器件以及被配置为选择性地迫使N级LUT内的多路复用级的过载元件 选择一个或多个LUT配置位输入或非LUT逻辑功能的输出作为LUT的输出。 在各种实施例中，非LUT功能可以包括加法，减法，乘法，除法，数字信号处理，存储器存储等
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公开(公告)号：US07587686B1
公开(公告)日：2009-09-08
申请号：US11497705
申请日：2006-08-01
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/64
摘要： Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and one or more clock gating circuits. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal and a clock enable signal to a plurality of predetermined locations on the device. A clock gating circuit, connected with the deterministic portion, may be placed at any of the predetermined locations, or at any location within predetermined areas associated with the predetermined locations. The clock gating circuit produces a gated clock signal output. A configurable portion and/or subportion distributes the gated clock signal output to logic elements. Depending on the value of the clock enable signal, operation of the logic elements may be suspended.
摘要翻译： 电路和方法使用时钟选通来降低结构化ASIC的某些部分的功耗。 时钟分配网络包括确定性部分，可配置部分和一个或多个时钟门控电路。 确定部分采用预定布置的导体段和缓冲器，用于将时钟信号和时钟使能信号分配到设备上的多个预定位置。 与确定性部分连接的时钟门控电路可以放置在任何预定位置处，或者与预定位置相关联的预定区域内的任何位置。 时钟选通电路产生门控时钟信号输出。 可配置部分和/或子部分将门控时钟信号输出分配给逻辑元件。 根据时钟使能信号的值，可能会暂停逻辑元件的操作。
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5.发明申请Field programmable gate array with integrated application specific integrated circuit fabric 有权具有集成专用集成电路结构的现场可编程门阵列公开(公告)号：US20090051387A1
公开(公告)日：2009-02-26
申请号：US11894283
申请日：2007-08-20
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译： 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。 定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。
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公开(公告)号：US5574893A
公开(公告)日：1996-11-12
申请号：US512600
申请日：1995-08-08
CPC分类号： G06F17/5022 , Y10S706/92
摘要： A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process. Since the dynamic device models are in the form of executable code, which can be directly read during the simulation process, the speed of operation of the simulation process is substantially increased, with a corresponding reduction in the total processing time required. In addition, the size of the simulator netlist is substantially reduced.
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公开(公告)号：US5477474A
公开(公告)日：1995-12-19
申请号：US969943
申请日：1992-10-29
CPC分类号： G06F17/5022 , Y10S706/92
摘要： A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process. Since the dynamic device models are in the form of executable code, which can be directly read during the simulation process, the speed of operation of the simulation process is substantially increased, with a corresponding reduction in the total processing time required. In addition, the size of the simulator netlist is substantially reduced.
摘要翻译： 一种用于改善计算机系统中的计算机逻辑模拟器的性能的方法，其中通过将表示逻辑设计的网络列表转换为模拟器网表来模拟逻辑设计的操作，并将预定的输入向量应用于代表 逻辑设计为了生成代表仿真器网表响应的输出向量。 将网络列表的部分以可执行代码的形式转换为动态设备模型，该可执行代码组装在动态设备模型文件中。 网络列表的剩余部分被转换为模拟器网表，其被存储在模拟器网表文件中。 动态设备模型和模拟器网表均用于执行仿真过程。 由于动态设备模型是可执行代码的形式，可以在仿真过程中直接读取，仿真过程的运行速度大大提高，同时减少了所需的总处理时间。 此外，模拟器网表的大小显着降低。
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公开(公告)号：US08612772B1
公开(公告)日：2013-12-17
申请号：US11490764
申请日：2006-07-20
IPC分类号： H04L9/32
CPC分类号： G06F21/76
摘要： Implementing a key and a protection circuit in a configurable device. A soft key associated with a protection circuit is combined with a user's electronic design in generating configuration data for download onto the configurable device. The placement and routing of the soft key is pseudo-randomly arranged with respect to the user's electronic design such that its placement and routing on the configurable device is substantially different for binary configuration data that is generated. Hiding the soft key and its connections to the protection circuit and assisting in protecting user electronic designs is achieved.
摘要翻译： 在可配置设备中实现密钥和保护电路。 与保护电路相关联的软键与用户的电子设计组合以产生用于下载到可配置设备上的配置数据。 软键的放置和布线相对于用户的电子设计伪随机布置，使得其在可配置设备上的放置和布线对于生成的二进制配置数据而言是显着不同的。 隐藏软键及其与保护电路的连接，并协助保护用户电子设计。
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9.发明授权公开(公告)号：US07275232B2
公开(公告)日：2007-09-25
申请号：US11097633
申请日：2005-04-01
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/505 , G06F2217/64
摘要： Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.
摘要翻译： 提供了可产生功能等同的现场可编程门阵列（“FPGA”）和结构化专用集成电路（“结构化ASIC”）的编译器流。 流可以包括反馈在任一流程期间执行的设计变换，使得另一流程的稍后的性能将必然包括相同的变换，由此有助于确保功能等同性。 流程可以包括中间结果的比较，以证明正在实现功能等同性。
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10.发明授权公开(公告)号：US07373631B1
公开(公告)日：2008-05-13
申请号：US10916305
申请日：2004-08-11
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/64
摘要： Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.
摘要翻译： 功能上等同于FPGA的结构化ASIC的合成方法利用FPGA的用户逻辑设计的综合。 针对FPGA技术合成的用户逻辑的几个相对较小的部分中的每一个针对结构化ASIC实现重新合成。 再合成可以不同地处理不同种类的逻辑部分。 例如，对于ASIC合成已知且可用于库的部分，可以从库中检索已知的ASIC合成。 可以对不可用的库合成的逻辑的其他部分执行更广泛的再合成（包括例如逻辑最小化和函数打包）。
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