公开(公告)号：US07563659B2

公开(公告)日：2009-07-21

申请号：US11003326

申请日：2004-12-06

Applicant: Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

Inventor： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC: H01L21/00

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using inductively coupled plasma chemical vapor deposition (ICP-CVD). After the ICP-CVD, excimer laser annealing (ELA) is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO2 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiO2 can be as high as 1011/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

Abstract translation: 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用电感耦合等离子体化学气相沉积（ICP-CVD）在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时进行准分子激光退火（ELA）。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2栅极绝缘层。 多晶硅的大晶粒尺寸约为3000或更大。 SiO2的界面陷阱密度高达1011 / cm2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US20080204434A1

公开(公告)日：2008-08-28

申请号：US11932195

申请日：2007-10-31

Applicant: Min-Cheol Lee ,  Dong-Gyun Ra

Inventor： Min-Cheol Lee ,  Dong-Gyun Ra

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G02F1/1345 ,  G02F1/13454 ,  G02F1/136286 ,  G09G2310/0218 ,  G09G2310/0221 ,  G09G2310/0275

Abstract: A display device includes a display panel, a first source driver chip and a connection section. The display panel includes a plurality of source lines, each of which is electrically connected to a plurality of pixels. The first source driver chip is electrically connected to a first group including a first of the source lines to output a data signal having a first polarity to the first source line. The connection section electrically connects the first source line to a last source line of the source lines to provide the data signal having the first polarity to the last source line without need for an additional source driver chip to drive the (mk+1)-th source line.

Abstract translation: 显示装置包括显示面板，第一源驱动器芯片和连接部。 显示面板包括多个源极线，每条源极电连接到多个像素。 第一源极驱动器芯片电连接到包括第一源极线的第一组，以将具有第一极性的数据信号输出到第一源极线。 连接部分将第一源极线连接到源极线的最后源极线，以将具有第一极性的数据信号提供给最后的源极线，而不需要额外的源极驱动器芯片来驱动第（mk + 1）个 源线。

公开(公告)号：US20080136809A1

公开(公告)日：2008-06-12

申请号：US11974035

申请日：2007-10-10

Applicant: Chang-Soo Lee ,  Young-Soon Lee ,  Min-Cheol Lee ,  Jang-Hyun Yeo ,  Seung-Hwan Moon

Inventor： Chang-Soo Lee ,  Young-Soon Lee ,  Min-Cheol Lee ,  Jang-Hyun Yeo ,  Seung-Hwan Moon

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G2310/0248 ,  G09G2310/0289 ,  G09G2320/0204

Abstract: An LCD corrects deviations in pixel kickback voltages caused by delays in gate driving signals. The LCD includes a timing controller generating first and second output enable signals, first and second level shifters respectively generating first and second gate clock pulses and inverted clock pulses, and first and second gate drivers respectively generating first and second gate driving signals. A precharge time of the first gate driving signals is controlled by the pulse width of the first output enable signal and a precharge time of the second gate driving signals is controlled by the pulse width of the second output enable signal.

Abstract translation: LCD校正由栅极驱动信号延迟引起的像素反冲电压的偏差。 LCD包括产生第一和第二输出使能信号的定时控制器，分别产生第一和第二栅极时钟脉冲和反相时钟脉冲的第一和第二电平移位器以及分别产生第一和第二栅极驱动信号的第一和第二栅极驱动器。 第一栅极驱动信号的预充电时间由第一输出使能信号的脉冲宽度控制，第二栅极驱动信号的预充电时间由第二输出使能信号的脉冲宽度控制。

公开(公告)号：US20080100560A1

公开(公告)日：2008-05-01

申请号：US11928466

申请日：2007-10-30

Applicant: Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

Inventor： Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/041

Abstract: In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.

Abstract translation: 在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号 通过输出端子输出到栅极导通电压。 缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。 缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。 因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。