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    System and method for creating and maintaining data records to improve accuracy thereof
    42.
    发明申请
    System and method for creating and maintaining data records to improve accuracy thereof 审中-公开
    用于创建和维护数据记录以提高其精度的系统和方法

    公开(公告)号：US20060112133A1

    公开(公告)日：2006-05-25

    申请号：US11259986

    申请日：2005-10-26

    Applicant: Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

    Inventor： Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

    IPC: G06F17/00 ,  G06F7/00

    CPC classification number: G06F16/9024

    Abstract: In one example, a system receives, from different sources, data having various formats, the received data is selected and combined in accordance with the invention to create accurate records. Specifically, the inventive system organizes the received data into uniform data records having a predetermined format. The data in the uniform data records is converted, if necessary, to conform to a predetermined nomenclature, resulting in normalized data records. The normalized data records are then processed to extract and/or deduce information desired by users.

    Abstract translation: 在一个示例中，系统从不同的源接收具有各种格式的数据，根据本发明选择和组合接收的数据以创建准确的记录。 具体地，本发明的系统将接收到的数据组织成具有预定格式的统一数据记录。 如果需要，统一数据记录中的数据被转换成符合预定的命名，导致归一化的数据记录。 然后处理归一化的数据记录以提取和/或推导出用户期望的信息。

    Tracking and monitoring system for opencast mines
    46.
    发明授权
    Tracking and monitoring system for opencast mines 有权
    露天矿的跟踪监测系统

    公开(公告)号：US08816850B2

    公开(公告)日：2014-08-26

    申请号：US13265585

    申请日：2010-03-29

    Applicant: Lakshmi Kanta Bandyopadhyay ,  Swades Kumar Chaulya ,  Pankaj Kumar Mishra

    Inventor： Lakshmi Kanta Bandyopadhyay ,  Swades Kumar Chaulya ,  Pankaj Kumar Mishra

    IPC: G08B21/00 ,  E21F17/18 ,  G01S5/02 ,  G08G1/16

    CPC classification number: G08G1/16 ,  E21F17/18 ,  G01S5/02 ,  G08G1/166

    Abstract: The tracking and monitoring system for opencast mines of the present invention enables continuously tracking and monitoring vehicles and moveable equipment in opencast mines using ZigBee-enabled active RFID devices forming a dynamic wireless network among them and other static and mobile ZigBee devices placed at strategic locations. The present invention provides a tracking and monitoring system for opencast mines comprises in combination of ZigBee-compliant devices (programmable to operate as end devices, routers and coordinators by hardware specific embedded software) and wireless sensor network software having various application modules for opencast mines. Use of the system of the present invention would help in maintaining computerized record and analysing the performance of costly shovels and dumpers deployed in opencast mines. This would help in optimising the placement of dumpers with each shovel depending on the change in working and dumping places. This would also help in maintaining computerise attendance of dumper operators and other personnel working in an opencast mine. This would further help in providing warning to the signal man and dumper operator, while dumper approaching close proximity to the signal man. This would help in establishing two-way message communication among the personnel engaged in an opencast mine. This would ultimately help in improving production, productivity and safety in opencast mine.

    Abstract translation: 本发明的露天矿的跟踪和监测系统能够使用启用了ZigBee的有源RFID设备在其中形成动态无线网络以及其他静态和移动的ZigBee设备在战略位置跟踪和监控车辆和可移动设备。 本发明提供了一种用于露天矿的跟踪和监测系统，其包括符合ZigBee的设备（可编程为通过硬件专用嵌入式软件作为终端设备，路由器和协调器进行操作）和具有用于露天矿的各种应用模块的无线传感器网络软件。 使用本发明的系统将有助于维持计算机记录并分析部署在露天煤矿中的昂贵的铲子和翻斗车的性能。 这将有助于根据工作和倾倒场所的变化优化每个铲子的自卸车的位置。 这也有助于维持从事露天煤矿的转储经营者和其他人员的电脑化。 这将有助于向信号人和翻斗车操作员提供警告，而翻斗车靠近信号人。 这将有助于在从事露天矿的人员之间建立双向信息沟通。 这将最终有助于提高露天矿的生产，生产力和安全性。

    Jitter reduction in high speed low core voltage level shifter
    47.
    发明授权
    Jitter reduction in high speed low core voltage level shifter 有权
    高速低电压电平转换器的抖动降低

    公开(公告)号：US08816748B2

    公开(公告)日：2014-08-26

    申请号：US13494188

    申请日：2012-06-12

    Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    IPC: H03L5/00

    CPC classification number: H03K3/356113 ,  H03K3/013

    Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The first supply has a higher voltage than the second supply.

    Abstract translation: 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第一个电源具有比第二个电源更高的电压。

    JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER
    48.
    发明申请
    JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER 有权
    高速低电压电平变换器中的抖动减少

    公开(公告)号：US20130328611A1

    公开(公告)日：2013-12-12

    申请号：US13494188

    申请日：2012-06-12

    Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

    IPC: H03L5/00

    CPC classification number: H03K3/356113 ,  H03K3/013

    Abstract: An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply.

    Abstract translation: 一种包括电平移位器电路和控制电路的装置。 电平移位器电路可以被配置为响应于（i）第一差分输入，（ii）第二差分输入和（iii）第一电源而产生差分输出。 电平移位器电路包括与第一电源一起工作的第一下拉晶体管对。 控制电路可以被配置为响应于（i）第一差分输入和（ii）第二电源而产生第二差分输入。 控制电路通常包括与第二电源一起工作的第二下拉晶体管对。 第二个电源具有比第一个电源更高的电压。

    Hybrid impedance compensation in a buffer circuit
    49.
    发明授权
    Hybrid impedance compensation in a buffer circuit 有权
    缓冲电路中的混合阻抗补偿

    公开(公告)号：US08598941B2

    公开(公告)日：2013-12-03

    申请号：US13165195

    申请日：2011-06-21

    Applicant: Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    Inventor： Dipankar Bhattacharya ,  Ashish V. Shukla ,  John Christopher Kriz ,  Makeshwar Kothandaraman ,  Pankaj Kumar ,  Pramod Parameswaran

    IPC: H01L37/00

    CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F1/56 ,  H03F2200/447

    Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

    Abstract translation: 用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。 监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。 监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态 缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。 控制电路用于产生作为第一控制信号的函数的一组数字控制位。 该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

    Method of and system for malicious software detection using critical address space protection
    50.
    发明授权
    Method of and system for malicious software detection using critical address space protection 有权
    使用关键地址空间保护的恶意软件检测方法和系统

    公开(公告)号：US08515075B1

    公开(公告)日：2013-08-20

    申请号：US12322220

    申请日：2009-01-29

    Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

    Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

    IPC: G06F21/00

    CPC classification number: G06F21/566

    Abstract: A method of identifying malicious code based on identifying software executing out of writable memory of the computer system. In one embodiment, the identification of the malicious code occurs when the code accesses a predetermined memory address. This address can reside in the address space of an application, a library, or an operating system component. In one embodiment, the access to the predetermined address generates an exception invoking exception handling code. The exception handling code checks the memory attributes of the code that caused the exception and determines whether the code was running in writeable memory.

    Abstract translation: 基于识别从计算机系统的可写入存储器执行的软件来识别恶意代码的方法。 在一个实施例中，当代码访问预定的存储器地址时，发生恶意代码的识别。 该地址可以驻留在应用程序，库或操作系统组件的地址空间中。 在一个实施例中，对预定地址的访问生成异常调用异常处理代码。 异常处理代码检查导致异常的代码的内存属性，并确定代码是否在可写内存中运行。

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