公开(公告)号：US06690604B2

公开(公告)日：2004-02-10

申请号：US10024901

申请日：2001-12-18

Applicant: Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

Inventor： Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

IPC: G11C700

CPC classification number: G11C7/12

Abstract: A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.

Abstract translation: 存储器电路，例如高速缓存或寄存器文件，其中保持器功能单元被数字地控制以补偿可变的亚阈值泄漏电流。

公开(公告)号：US20200098824A1

公开(公告)日：2020-03-26

申请号：US16142040

申请日：2018-09-26

Applicant: Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

Inventor： Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20190057727A1

公开(公告)日：2019-02-21

申请号：US16160955

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G11C7/10 ,  G11C5/04 ,  G06F12/06

Abstract: Techniques and mechanisms for configuring a memory device to perform a sequence of in-memory computations. In an embodiment, a memory device includes a memory array and circuitry, coupled thereto, to perform data computations based on the data stored at the memory array. Based on instructions received at the memory device, control circuitry is configured to enable an automatic performance of a sequence of operations. In another embodiment, the memory device is coupled in an in-series arrangement of other memory devices to provide a pipeline circuit architecture. The memory devices each function as a respective stage of the pipeline circuit architecture, where the stages each perform respective in-memory computations. Some or all such stages each provide a different respective layer of a neural network.

公开(公告)号：US20190057304A1

公开(公告)日：2019-02-21

申请号：US16160800

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06N3/063 ,  G06N3/04

Abstract: The present disclosure is directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

公开(公告)号：US09544141B2

公开(公告)日：2017-01-10

申请号：US13996544

申请日：2011-12-29

Applicant: Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

Inventor： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

IPC: H04L29/06 ,  H04L9/08

CPC classification number: H04L9/0891 ,  G09C1/00 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L2209/12

Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.

Abstract translation: 本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置。 处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。 硬件密钥可用于加密诸如秘密密钥的密钥。 加密密钥可以存储在处理器的存储器中。 可以验证加密的密钥。 可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

公开(公告)号：US07519646B2

公开(公告)日：2009-04-14

申请号：US11586810

申请日：2006-10-26

Applicant: Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

IPC: G06F7/52

CPC classification number: G06F7/5324 ,  G06F2207/3828

Abstract: A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

Abstract translation: 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

公开(公告)号：US07477171B2

公开(公告)日：2009-01-13

申请号：US11729191

申请日：2007-03-27

Applicant: Sanu K. Mathew ,  Ram Krishnamurthy

Inventor： Sanu K. Mathew ,  Ram Krishnamurthy

IPC: H03M7/04

CPC classification number: H03M7/12

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract translation: 本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

公开(公告)号：US20080238736A1

公开(公告)日：2008-10-02

申请号：US11729191

申请日：2007-03-27

Applicant: Sanu K. Mathew ,  Ram Krishnamurthy

Inventor： Sanu K. Mathew ,  Ram Krishnamurthy

IPC: H03M7/12

CPC classification number: H03M7/12

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract translation: 本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

公开(公告)号：US20080181295A1

公开(公告)日：2008-07-31

申请号：US11699241

申请日：2007-01-29

Applicant: Mark Anders ,  Himanshu Kaul ,  Sanu Mathew ,  Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

Inventor： Mark Anders ,  Himanshu Kaul ,  Sanu Mathew ,  Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

IPC: H04B1/66

CPC classification number: H04N19/436 ,  H04N19/43

Abstract: In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括使用冗余二进制数学压缩视频数据的方法。 描述和要求保护其他实施例。

公开(公告)号：US07380099B2

公开(公告)日：2008-05-27

申请号：US10956164

申请日：2004-09-30

Applicant: Sanu K. Mathew ,  Mark A. Anders ,  Sarvesh H. Kulkarni ,  Ram Krishnamurthy

Inventor： Sanu K. Mathew ,  Mark A. Anders ,  Sarvesh H. Kulkarni ,  Ram Krishnamurthy

IPC: G06F12/00

CPC classification number: G06F7/507 ,  G06F7/508

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract translation: 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。