Electronic apparatus and method for controlling thereof

    公开(公告)号:US12131738B2

    公开(公告)日:2024-10-29

    申请号:US17944401

    申请日:2022-09-14

    IPC分类号: G10L15/22 G10L15/02 G10L15/26

    摘要: An electronic apparatus is disclosed. The electronic apparatus may include a microphone; a communication interface; a memory configured to store at least one instruction; and a processor configured to execute the at least one instruction to: obtain a user voice input for registering a wake-up voice input via the microphone; input the user voice input into a trained neural network model to obtain a first feature vector corresponding to text included in the user voice input; receive a verification data set determined based on information related to the text included in the user voice input from an external server via the communication interface; input a verification voice input included in the verification data set into the trained neural network model to obtain a second feature vector corresponding to the verification voice input; and identify whether to register the user voice input as the wake-up voice input based on a similarity between the first feature vector and the second feature vector.

    Electronic device including preview images for background screen for flexible display and control method thereof

    公开(公告)号:US12131676B2

    公开(公告)日:2024-10-29

    申请号:US18181262

    申请日:2023-03-09

    IPC分类号: G09G3/00

    摘要: An electronic device comprises a display having a display area, wherein a size of the display area visually exposed in a first state of the electronic device is reduced and a size of the display area visually exposed in a second state of the electronic device is enlarged, and a processor operatively connected to the display, wherein the processor may be configured to acquire state information of the electronic device, successively display a first preview image and a second preview images on the display, based on the state information of the electronic device, wherein the first preview image includes a first area of a specified image and corresponds to a preview image of a background screen in the first state, wherein the second preview image comprises a second area including the first area and a further area extending from the first area, and corresponds to a preview image of a background screen in the second state, and specify the image as a background screen, based on a first user input.

    Method and apparatus with neural network distributed processing

    公开(公告)号:US12131254B2

    公开(公告)日:2024-10-29

    申请号:US16919661

    申请日:2020-07-02

    发明人: Jiseung Jang

    IPC分类号: G06N3/08 G06N3/04

    CPC分类号: G06N3/08 G06N3/04

    摘要: A processor-implemented neural network distributed processing method includes: obtaining a first operation cost of a neural network according to a distribution strategy based on a plurality of operation devices; generating an operation configuration corresponding to the neural network based on the obtained first operation cost; performing a reduction operation on the generated operation configuration; and processing an operation of the neural network based on a reduced operation configuration obtained by performing the reduction operation.

    Storage device
    46.
    发明授权

    公开(公告)号:US12131054B2

    公开(公告)日:2024-10-29

    申请号:US17877297

    申请日:2022-07-29

    IPC分类号: G06F3/06 G06F1/18

    摘要: A storage device includes a memory module including a memory device, a module board including a memory controller configured to control the memory device, and a memory connector disposed on one side of the module board. The storage device also includes a first enclosure disposed on a first surface of the memory module, a second enclosure disposed on a second surface opposite to the first surface of the memory module, and a first sensor disposed on the first enclosure and configured to detect a state and provide a signal for the state to the memory controller. The first enclosure includes a first long side extending in a first direction and a first short side extending in a second direction perpendicular to the first direction. A ratio of the first long side to the first short side ranges from 1.2 to 3.5.

    Module substrate for semiconductor module, semiconductor module and test socket for testing the same

    公开(公告)号:US12130306B2

    公开(公告)日:2024-10-29

    申请号:US17884661

    申请日:2022-08-10

    IPC分类号: G01R1/04 G01R31/28

    摘要: A module substrate for a semiconductor module includes: a wiring substrate having an upper surface and a lower surface opposite to the upper surface, wherein the wiring substrate includes a circuit wiring and a plurality of via holes extending from the upper surface to the lower surface in a thickness direction; a plurality of test terminals respectively provided on the via holes and electrically connected to the circuit wiring, and a fastening thin film provided on the wiring substrate and covering the via holes, wherein the fastening thin film has a predetermined thickness such that a portion of the fastening thin film is penetrated when an interface is pin is inserted into the portion of the fastening thin film through the via hole from the upper surface, and the portion of the penetrated fastening thin film holds the penetrating interface inspection pin.

    SEMICONDUCTOR MEMORY DEVICE
    50.
    发明公开

    公开(公告)号:US20240357810A1

    公开(公告)日:2024-10-24

    申请号:US18757708

    申请日:2024-06-28

    IPC分类号: H10B43/20 H10B43/10

    CPC分类号: H10B43/20 H10B43/10

    摘要: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.