公开(公告)号：US20230189002A1

公开(公告)日：2023-06-15

申请号：US18065514

申请日：2022-12-13

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: H04W12/47 ,  H04W12/06 ,  H04W12/033

CPC classification number: H04W12/47 ,  H04W12/06 ,  H04W12/033

Abstract: In an embodiment a method for implementing a NFC transaction between a mobile terminal and a distant module is disclosed. The terminal includes a processor hosting an application configured to establish the NFC transaction, a near-field communication module, and a secure element distinct from the processor. The method includes storing, by the near-field communication module in the secure element, first data from the distant module, sending, by the near-field communication module, second data to the application notifying it that the first data have been stored in the secure element and requesting, by the application, the first data from the secure element.

公开(公告)号：US20230186295A1

公开(公告)日：2023-06-15

申请号：US17992392

申请日：2022-11-22

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: G06Q20/38 ,  G06Q20/32 ,  G06Q20/40

CPC classification number: G06Q20/3829 ,  G06Q20/3278 ,  G06Q20/405 ,  G06Q2220/00

Abstract: The present description concerns a method of implementation of an NFC transaction between a mobile terminal and a distant module. The terminal includes a processor hosting an application establishing the NFC transaction, a near-field communication module, and a secure element distinct from the processor. The method includes at least the following successive steps: (a) the near-field communication module sends, to the first application, first data sent by the distant module and ciphered by the secure element; and (b) the first application asks the secure element to decipher the first data.

公开(公告)号：US20230170938A1

公开(公告)日：2023-06-01

申请号：US18153958

申请日：2023-01-12

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Chia Hao CHEN ,  Nicolas CORDIER

IPC: H04B5/00 ,  H02J50/80 ,  H02J50/90 ,  H02J50/10

CPC classification number: H04B5/0037 ,  H02J50/80 ,  H02J50/90 ,  H02J50/10 ,  H04B5/0031 ,  H04B5/0081

Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

公开(公告)号：US20230162764A1

公开(公告)日：2023-05-25

申请号：US17902171

申请日：2022-09-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/135 ,  H03K5/1534

CPC classification number: G11C7/1066 ,  G11C7/222 ,  H03K5/135 ,  H03K5/1534

Abstract: The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.

公开(公告)号：US20230155369A1

公开(公告)日：2023-05-18

申请号：US18157737

申请日：2023-01-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Ravinder KUMAR ,  Nicolas DEMANGE

IPC: H02H3/20 ,  H02H1/00

CPC classification number: H02H3/20 ,  H02H1/0007

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US20230134063A1

公开(公告)日：2023-05-04

申请号：US17970351

申请日：2022-10-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Rosalia GERMANA-CARPINETO ,  Lia MASOERO

IPC: H01L29/423 ,  H01L29/78

Abstract: The present description concerns an electronic device comprising a semiconductor substrate, transistors having their gates contained in first trenches extending in the substrate, and at least one electronic component, different from a transistor, at least partly formed in a first semiconductor region contained in a second trench extending in the semiconductor substrate parallel to the first trenches.

公开(公告)号：US11640972B2

公开(公告)日：2023-05-02

申请号：US17591233

申请日：2022-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

公开(公告)号：US20230126011A1

公开(公告)日：2023-04-27

申请号：US18045097

申请日：2022-10-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand ,  Jean-Francois Link

IPC: G06T1/60 ,  G06F12/10 ,  G06F12/0802

Abstract: In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.

公开(公告)号：US11637947B2

公开(公告)日：2023-04-25

申请号：US16669951

申请日：2019-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand

IPC: H04N5/06 ,  G09G5/00 ,  H04N5/232 ,  G06F1/04 ,  G06F3/041 ,  H04N5/04

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

公开(公告)号：US11621222B2

公开(公告)日：2023-04-04

申请号：US17173275

申请日：2021-02-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/66 ,  H01L23/522 ,  H01L21/762 ,  H01L27/08

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.