公开(公告)号：US06304960B1

公开(公告)日：2001-10-16

申请号：US09130380

申请日：1998-08-06

Applicant: Tse-Yu Yeh ,  Michael Paul Corwin ,  Judge K. Arora ,  Sujat Jamil ,  Sailesh Kottapalli

Inventor： Tse-Yu Yeh ,  Michael Paul Corwin ,  Judge K. Arora ,  Sujat Jamil ,  Sailesh Kottapalli

IPC: G06F938

CPC classification number: G06F9/3885 ,  G06F9/30072 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3861

Abstract: A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the determined target addresses is selected, using predicted branch directions. The selected target address is compared with a predicted target address, and resolved branch directions are compared with predicted branch directions. A misprediction is indicated if either comparison fails.

Abstract translation: 用于验证分支指令簇的分支预测的系统包括地址验证模块和条件验证模块。 地址验证模块确定集群中分支的目标地址。 使用预测的分支方向选择确定的目标地址之一。 将所选择的目标地址与预测的目标地址进行比较，并将分辨的分支方向与预测的分支方向进行比较。 如果比较失败，则会显示错误预测。

公开(公告)号：US20180081808A1

公开(公告)日：2018-03-22

申请号：US13808595

申请日：2012-01-06

Applicant: Vedaraman GEETHA ,  Jeffrey D. CHAMBERLAIN ,  Sailesh KOTTAPALLI ,  Ganesh KUMAR ,  Henk G. NEEFS ,  Neil J. ACHTMAN ,  Bongjin JUNG

Inventor： Vedaraman GEETHA ,  Jeffrey D. CHAMBERLAIN ,  Sailesh KOTTAPALLI ,  Ganesh KUMAR ,  Henk G. NEEFS ,  Neil J. ACHTMAN ,  Bongjin JUNG

IPC: G06F12/0817 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F2212/622

Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

公开(公告)号：US20150178206A1

公开(公告)日：2015-06-25

申请号：US14136131

申请日：2013-12-20

Applicant: Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

Inventor： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0815

Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Abstract translation: 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

公开(公告)号：US08656115B2

公开(公告)日：2014-02-18

申请号：US12860340

申请日：2010-08-20

Applicant: Sailesh Kottapalli ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

Inventor： Sailesh Kottapalli ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

公开(公告)号：US20130275995A1

公开(公告)日：2013-10-17

申请号：US13912777

申请日：2013-06-07

Applicant: Sailesh Kottapalli ,  John H. Crawford

Inventor： Sailesh Kottapalli ,  John H. Crawford

IPC: G06F9/52

CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US08495091B2

公开(公告)日：2013-07-23

申请号：US13175772

申请日：2011-07-01

Applicant: Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

Inventor： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

IPC: G06F17/30

CPC classification number: G06F13/4022

Abstract: Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

Abstract translation: 描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。 在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。 还公开了其他实施例。

公开(公告)号：US08473963B2

公开(公告)日：2013-06-25

申请号：US13069684

申请日：2011-03-23

Applicant: Sailesh Kottapalli ,  John H. Crawford

Inventor： Sailesh Kottapalli ,  John H. Crawford

IPC: G06F9/46 ,  G06F9/30 ,  G06F7/38 ,  G06F13/00

CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US07996644B2

公开(公告)日：2011-08-09

申请号：US11026316

申请日：2004-12-29

Applicant: Sailesh Kottapalli

Inventor： Sailesh Kottapalli

IPC: G06F12/02

CPC classification number: G06F12/084 ,  G06F12/0864 ,  G06F12/126

Abstract: An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor sharing access to a cache is assigned a static portion of the cache and a dynamic portion. The resource is blocked from victimizing static portions assigned to other resources, yet, allowed to victimize the static portion assigned to the resource and the dynamically shared portion. If the resource does not access the cache enough times over a period of time, the static portion assigned to the resource is reassigned to the dynamically shared portion.

Abstract translation: 这里描述了用于公平地访问具有多个资源（例如多个核心，多个线程或两者）的多个资源的共享高速缓存的装置和方法。 分配对高速缓存的访问的微处理器内的资源被分配有高速缓存的静态部分和动态部分。 该资源被阻止从分配给其他资源的静态部分受到伤害，但是允许资源分配给动态共享部分的静态部分。 如果资源在一段时间内没有足够的时间访问缓存，则分配给资源的静态部分被重新分配给动态共享部分。

公开(公告)号：US20110161585A1

公开(公告)日：2011-06-30

申请号：US12647458

申请日：2009-12-26

Applicant: SAILESH KOTTAPALLI ,  Jeffrey Baxter ,  James R. Vash ,  Bongjin Jung ,  Andrew Y. Sun

Inventor： SAILESH KOTTAPALLI ,  Jeffrey Baxter ,  James R. Vash ,  Bongjin Jung ,  Andrew Y. Sun

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0831 ,  Y02D10/13

Abstract: Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who stores the first data in an alternative modified state. Other embodiments are also described.

Abstract translation: 描述了在不同处理器的高速缓存中有效处理非所有权负载请求达到修改行（M行）的方法和装置。 在一个实施例中，第一代理改变第一数据的状态并将其转发到以备选修改状态存储第一数据的第二请求代理。 还描述了其它实施例。

公开(公告)号：US07181590B2

公开(公告)日：2007-02-20

申请号：US10650335

申请日：2003-08-28

Applicant: Sailesh Kottapalli ,  Nadeem H. Firasta

Inventor： Sailesh Kottapalli ,  Nadeem H. Firasta

IPC: G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/1036

Abstract: A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.

Abstract translation: 公开了一种允许多线程处理器使用翻译后备缓冲器在预先验证的高速缓存中的不同线程上共享页面的方法和系统。 多线程处理器搜索翻译后备缓冲区以尝试匹配虚拟内存地址。 如果没有找到匹配的有效虚拟内存地址，则检索新的翻译，并搜索匹配的物理内存地址的翻译后备缓冲区。 如果找到匹配的物理内存地址，则使用新的翻译覆盖旧的翻译。 多线程处理器可以执行切换事件多线程或同时多线程。 如果同时执行多线程，则每个线程的访问权限与翻译相关联。