公开(公告)号：US12261470B2

公开(公告)日：2025-03-25

申请号：US18299377

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangun Bang ,  Dongjo Kim ,  Jinsoo Lee ,  Woonhyung Heo ,  Dongjoon Kim ,  Sungeun Lee

IPC: H02J7/00 ,  H04B1/3827 ,  H04B3/02

Abstract: A portable device includes: a modem configured to perform power line communication with a charger external to the portable device; and a charging circuit configured to, from first power provided by the charger, charge a battery and supply power to an electrical load, wherein the charging circuit is further configured to cut off the supply of the first power to the electrical load and supply second power from the battery to the electrical load.

公开(公告)号：US12261208B2

公开(公告)日：2025-03-25

申请号：US18538575

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee Park ,  Myunggil Kang ,  Uihui Kwon ,  Seungkyu Kim ,  Ahyoung Kim ,  Youngseok Song

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US12261204B2

公开(公告)日：2025-03-25

申请号：US18615049

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mun Hyeon Kim ,  Kern Rim ,  Dae Won Ha

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

公开(公告)号：US12261181B2

公开(公告)日：2025-03-25

申请号：US18167972

申请日：2023-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woonbae Kim

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L23/02

Abstract: A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is electrically connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer. The joining structure may overlap the terminal pad. The spacer is between the transparent substrate and the terminal pad.

公开(公告)号：US12261166B2

公开(公告)日：2025-03-25

申请号：US18140115

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungkyu Chae ,  Kwanyoung Chun ,  Yoonjin Kim

IPC: H01L27/02

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

公开(公告)号：US12261120B2

公开(公告)日：2025-03-25

申请号：US17391445

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin Lee

IPC: H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

公开(公告)号：US12261103B2

公开(公告)日：2025-03-25

申请号：US17647144

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.

公开(公告)号：US12261093B2

公开(公告)日：2025-03-25

申请号：US17883726

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Jongbo Shim ,  Hwanpil Park ,  Jangwoo Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

公开(公告)号：US12261021B2

公开(公告)日：2025-03-25

申请号：US17719680

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Bae Kim ,  Ji Hwan Kim ,  Hyong Seo Yoon ,  Sang Ki Nam ,  Hyun Jae Lee ,  Myung Geun Jeong

IPC: H01J37/32

Abstract: A substrate treatment apparatus including a chamber; a lower electrode in the chamber, wherein the substrate is on the lower electrode; an upper electrode in the chamber, and above the lower electrode; a pulse signal generator configured to generate a pulse signal; and a bias power supply configured to generate bias power having a pulsed non-sinusoidal waveform using the pulse signal, and supply the generated bias power to the lower electrode, wherein the bias power supply includes a DC power generator configured to receive the pulse signal and generate a direct-current (DC) voltage subjected to feedforward compensation based on the pulse signal; and a modulator configured to generate a power signal having a non-sinusoidal waveform using the DC voltage, and filter the power signal using the pulse signal to generate the bias power having the pulsed non-sinusoidal waveform.

公开(公告)号：US12260923B2

公开(公告)日：2025-03-25

申请号：US17820280

申请日：2022-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunee Lee ,  Jongyeol Park

IPC: G11C29/12 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, an address decoder, a leakage detector and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The leakage detector is commonly coupled to the plurality of mats at a sensing node in the address decoder. The control circuit performs a first leakage detection operation on M mats selected from the mats to determine a leakage of at least a portion of word-lines of the M mats in an N multi-mat mode, in response to the leakage of at least the portion of word-lines of the M mats being detected based on a result of the first leakage detection operation, inhibits at least one mat of the M mats, and performs a second leakage detection operation on at least one target mat from among the M mats except the inhibited mat.