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    DISPLACEMENT DESORPTION PROCESS FOR LIGHT OLEFIN SEPARATION
    42.
    发明申请
    DISPLACEMENT DESORPTION PROCESS FOR LIGHT OLEFIN SEPARATION 有权
    用于轻油分离的位移解吸过程

    公开(公告)号：US20130206581A1

    公开(公告)日：2013-08-15

    申请号：US13819007

    申请日：2011-08-26

    Applicant: Jong Nam Kim ,  Jong Ho Park ,  Hee Tae Beum ,  Seong Jun Lee ,  Jang Jae Lee ,  Dong Wook Kim ,  Chang Hyun Ko ,  Sang Sup Han ,  Soon Haeng Cho

    Inventor： Jong Nam Kim ,  Jong Ho Park ,  Hee Tae Beum ,  Seong Jun Lee ,  Jang Jae Lee ,  Dong Wook Kim ,  Chang Hyun Ko ,  Sang Sup Han ,  Soon Haeng Cho

    IPC: C07C7/00

    CPC classification number: C07C7/005 ,  B01D53/04 ,  B01D2253/108 ,  B01D2256/24 ,  B01D2257/7022 ,  B01D2259/40086 ,  B01D2259/404 ,  C07C7/04 ,  C07C7/13 ,  Y02P30/464 ,  C07C11/02 ,  C07C11/04 ,  C07C11/06

    Abstract: A process and apparatus for separating an olefin from mixed gases containing light olefins is provided. The process includes adsorbing the olefin of an olefin-containing mixed gas in an adsorption column packed with an adsorbent selectively adsorbing the olefin; discharging gases other than the olefin through the outlet of the adsorption column; desorbing the adsorbed olefin by displacement using a desorbent, and separating the olefin from the desorbent, thereby producing a high-purity olefin. The apparatus includes adsorption columns packed with an adsorbent selectively adsorbing an olefin, and at least two distillation columns for separating an olefin/desorbent mixture and an olefin poor stream/desorbent into their components. If the olefin concentration of the off-gas from an olefin rinse step is higher than that of a raw material gas, recovering the olefin from the off-gas is carried out before or after the adsorption step.

    Abstract translation: 提供了一种用于从含有轻质烯烃的混合气体中分离烯烃的方法和装置。 该方法包括在填充有选择性吸附烯烃的吸附剂的吸附塔中吸附含烯烃混合气体的烯烃; 通过吸附塔的出口排出除烯烃以外的气体; 使用解吸剂通过置换解吸吸附的烯烃，并从解吸剂中分离烯烃，从而产生高纯度烯烃。 该装置包括填充有选择性吸附烯烃的吸附剂的吸附塔和用于将烯烃/脱附剂混合物和烯烃不良物流/解吸剂分离成其组分的至少两个蒸馏塔。 如果来自烯烃漂洗步骤的废气的烯烃浓度高于原料气体的烯烃浓度，则在吸附步骤之前或之后进行从废气中回收烯烃。

    DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
    44.
    发明申请
    DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE 审中-公开
    显示基板，显示面板和显示设备

    公开(公告)号：US20120127148A1

    公开(公告)日：2012-05-24

    申请号：US13283409

    申请日：2011-10-27

    Applicant: Seong-Jun Lee ,  Jin-Oh Park ,  Mu-Kyung Jeon ,  Yong-Kyu Jang ,  Dong-Hoon Lee ,  Chi-Woo Kim

    Inventor： Seong-Jun Lee ,  Jin-Oh Park ,  Mu-Kyung Jeon ,  Yong-Kyu Jang ,  Dong-Hoon Lee ,  Chi-Woo Kim

    IPC: G06F3/038 ,  G09G3/36

    CPC classification number: G02F1/134363 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/134372 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2320/0276 ,  G09G2320/0673

    Abstract: A display substrate includes an insulating substrate, a first gate line, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode. The insulating substrate includes a first pixel region and a second pixel region located at a first direction from the first pixel region. The first gate line extends in a second direction crossing the first direction on the insulating substrate. The first and the second lower electrodes are in the first and the second pixel regions, respectively. The first upper electrode overlaps the first lower electrode in the first pixel region and includes a first slit pattern extending in a third direction different from the first and the second directions. The second upper electrode overlaps the second lower electrode in the second pixel region and includes a second slit pattern extending in a fourth direction different from the first to third directions.

    Abstract translation: 显示基板包括绝缘基板，第一栅极线，第一下部电极，第二下部电极，第一上部电极和第二上部电极。 绝缘基板包括位于距第一像素区域的第一方向的第一像素区域和第二像素区域。 第一栅极线在与绝缘基板上的第一方向交叉的第二方向上延伸。 第一和第二下部电极分别位于第一和第二像素区域中。 第一上电极与第一像素区域中的第一下电极重叠，并且包括沿与第一和第二方向不同的第三方向延伸的第一狭缝图案。 第二上电极与第二像素区域中的第二下电极重叠，并且包括沿与第一至第三方向不同的第四方向延伸的第二狭缝图案。

    Semiconductor device
    46.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07952405B2

    公开(公告)日：2011-05-31

    申请号：US12493712

    申请日：2009-06-29

    Applicant: Seong-Jun Lee

    Inventor： Seong-Jun Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0812

    Abstract: A semiconductor device for providing a reliable data valid window includes a drive control unit configured to output a driving power control signal in response to an internal clock and a command signal; a sub-drive voltage supply unit configured to supply sub-drive voltages; a main drive unit configured to generate a delay-locked loop (DLL) clock by driving the internal clock with a main drive voltage; a sub-drive unit configured to drive the internal clock with the sub-drive voltage in response to the driving power control signal; and a data output driver configured to drive and output a data signal in sync with the DLL clock, wherein the main drive unit and the sub-drive unit share their output terminal.

    Abstract translation: 用于提供可靠数据有效窗口的半导体器件包括：驱动控制单元，被配置为响应于内部时钟和命令信号输出驱动功率控制信号; 副驱动电压供给部，被配置为提供副驱动电压; 主驱动单元，被配置为通过以主驱动电压驱动内部时钟来产生延迟锁定环（DLL）时钟; 子驱动单元，被配置为响应于驱动功率控制信号而以副驱动电压驱动内部时钟; 以及数据输出驱动器，被配置为与DLL时钟同步地驱动和输出数据信号，其中主驱动单元和副驱动单元共享其输出端子。

    Clock synchronization circuit and clock synchronization method
    48.
    发明授权
    Clock synchronization circuit and clock synchronization method 失效
    时钟同步电路和时钟同步方法

    公开(公告)号：US07701266B2

    公开(公告)日：2010-04-20

    申请号：US11964821

    申请日：2007-12-27

    Applicant: Seong Jun Lee

    Inventor： Seong Jun Lee

    IPC: H03L7/00

    CPC classification number: H03L7/0812

    Abstract: A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage.

    Abstract translation: 提出了一种产生与外部时钟同步的内部时钟的时钟同步电路和时钟同步方法。 电路和方法包括时钟使能控制电路，其产生由电源电压和掉电信号控制的时钟使能控制信号。 电路和方法还包括时钟发生电路，其接收输入时钟，该输入时钟使用时钟使能控制信号使用输入时钟选择性地产生与外部时钟同步的内部时钟。 于是，通过根据在掉电模式下电源电压是否变化来选择性地执行相位更新操作，可以防止锁定故障。 此外，通过根据电源电压的可变幅度控制相位更新时间，可以减少电流消耗。

    Apparatus and method of controlling operation frequency in DLL circuit
    49.
    发明授权
    Apparatus and method of controlling operation frequency in DLL circuit 有权
    控制DLL电路工作频率的装置及方法

    公开(公告)号：US07573312B2

    公开(公告)日：2009-08-11

    申请号：US11826653

    申请日：2007-07-17

    Applicant: Seong Jun Lee

    Inventor： Seong Jun Lee

    IPC: H03K3/00

    CPC classification number: H03L7/0812

    Abstract: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.

    Abstract translation: 倍频器增加外部时钟的频率，并输出高频外部时钟。 周期确定器确定是否经过了外部时钟的预定周期并输出周期确定信号。 频率选择器在上电信号和周期确定信号的控制下选择性地将外部时钟或高频外部时钟发送到时钟输入缓冲器。

    Internal voltage generator and semiconductor memory device having the same, and method of generating internal voltage
    50.
    发明授权
    Internal voltage generator and semiconductor memory device having the same, and method of generating internal voltage 有权
    具有相同的内部电压发生器和半导体存储器件以及产生内部电压的方法

    公开(公告)号：US07535307B2

    公开(公告)日：2009-05-19

    申请号：US11633057

    申请日：2006-12-04

    Applicant: Seong Jun Lee

    Inventor： Seong Jun Lee

    IPC: H03B1/00 ,  H03K3/01

    CPC classification number: H03K5/00006 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222 ,  H02M3/07

    Abstract: An internal voltage generator includes an oscillator, a cycle control unit and a voltage generator. The oscillator periodically generates a pulse-shaped oscillation signal. The cycle control unit bypasses the oscillation signal to an output node, or selectively controls the cycle of the oscillation signal and output a controlled oscillation signal to the output node. The voltage generator generates an internal voltage in response to the oscillation signal or the controlled oscillation signal received through the output node. The cycle of the controlled oscillation signal is shorter than that of the oscillation signal. The operating speed of the voltage generator when receiving the controlled oscillation signal is faster than that of the voltage generator when receiving the oscillation signal.

    Abstract translation: 内部电压发生器包括振荡器，周期控制单元和电压发生器。 振荡器周期性地产生脉冲振荡信号。 循环控制单元将振荡信号旁路到输出节点，或选择性地控制振荡信号的周期，并将受控振荡信号输出到输出节点。 电压发生器响应于通过输出节点接收的振荡信号或受控振荡信号产生内部电压。 受控振荡信号的周期比振荡信号的周期短。 当接收到受控振荡信号时，电压发生器的工作速度比接收振荡信号时的电压发生器的工作速度要快。

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