公开(公告)号：US07378831B1

公开(公告)日：2008-05-27

申请号：US11624392

申请日：2007-01-18

Applicant: Keith A. Jenkins ,  Seongwon Kim

Inventor： Keith A. Jenkins ,  Seongwon Kim

IPC: G01R19/00 ,  G01R29/02 ,  H03H11/26

CPC classification number: G01R31/3016

Abstract: A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Abstract translation: 提供了一种用于确定组件的延迟时间间隔的系统和方法。 该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。 该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

公开(公告)号：US07301320B2

公开(公告)日：2007-11-27

申请号：US11040225

申请日：2005-01-21

Applicant: Daniel M. Dreps ,  Seongwon Kim ,  Michael A. Sperling

Inventor： Daniel M. Dreps ,  Seongwon Kim ,  Michael A. Sperling

IPC: G05F5/00 ,  H02J1/02

CPC classification number: H03K5/08 ,  G01R19/16552 ,  G01R29/26

Abstract: The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.

Abstract translation: 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。 这具有以不需要校准的方式直接感测电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

公开(公告)号：US20070038404A1

公开(公告)日：2007-02-15

申请号：US11546165

申请日：2006-10-11

Applicant: Mohit Kapur ,  Seongwon Kim

Inventor： Mohit Kapur ,  Seongwon Kim

IPC: G06F19/00

CPC classification number: G01R31/31725 ,  H03K2005/00039 ,  H03K2005/00156

Abstract: A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

Abstract translation: 提供了使用XOR门作为延迟元件的可测试的数字延迟线。 使用XOR门可以独立控制多路复用器的每个输入。 通过测试输入可以实现每个延迟元件，多路复用器输入可以在测试期间分配任何值，从而为延迟线提供非常鲁棒的模式故障覆盖。 异或门可由三个限流逆变器组成。 参考电压发生器在源极电压，偏置电压和接地之间产生恒定电压。 这些恒定电压决定通过限流逆变器的电流量。 选择一组不同的参考电压可编程在限流逆变器中流动的不同电流。 该可编程电流导致每个XOR门延迟元件引入可编程单位延迟。

公开(公告)号：US20060247880A1

公开(公告)日：2006-11-02

申请号：US11117924

申请日：2005-04-29

Applicant: Mohit Kapur ,  Seongwon Kim

Inventor： Mohit Kapur ,  Seongwon Kim

IPC: G01R31/00

CPC classification number: G01R31/31725 ,  H03K2005/00039 ,  H03K2005/00156

Abstract: A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

Abstract translation: 提供了使用XOR门作为延迟元件的可测试的数字延迟线。 使用XOR门可以独立控制多路复用器的每个输入。 通过测试输入可以实现每个延迟元件，多路复用器输入可以在测试期间分配任何值，从而为延迟线提供非常鲁棒的模式故障覆盖。 异或门可由三个限流逆变器组成。 参考电压发生器在源极电压，偏置电压和接地之间产生恒定电压。 这些恒定电压决定通过限流逆变器的电流量。 选择一组不同的参考电压可编程在限流逆变器中流动的不同电流。 该可编程电流导致每个XOR门延迟元件引入可编程单位延迟。

公开(公告)号：US20060176096A1

公开(公告)日：2006-08-10

申请号：US11056798

申请日：2005-02-10

Applicant: Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Robert Reese ,  Hector Saenz ,  Michael Sperling

Inventor： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Robert Reese ,  Hector Saenz ,  Michael Sperling

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013

Abstract: A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias voltage generator and the delay element are included in a delay line which facilitates the providing of a delay that is insensitive to voltage fluctuations.

Abstract translation: 提供了电源电压不敏感延迟元件，其使数字信号由于电源漏洞而被延迟而没有变化。 使用由耦合到延迟元件的偏置电压发生器产生的偏置电压，延迟元件的晶体管限制电流。 偏置电压发生器和延迟元件包括在延迟线中，这有助于提供对电压波动不敏感的延迟。

公开(公告)号：US20060176080A1

公开(公告)日：2006-08-10

申请号：US11054831

申请日：2005-02-10

Applicant: Michael Sperling ,  Seongwon Kim ,  Paul Muench ,  Hector Saenz

Inventor： Michael Sperling ,  Seongwon Kim ,  Paul Muench ,  Hector Saenz

IPC: H03K19/084

CPC classification number: H03K17/693 ,  H03K17/162

Abstract: CMOS circuitry used to multiplex between data inputs suffers from high sensitivity to power supply noise, resulting in delay variations. By utilizing current controlled inverters in a multiplexer structure, power supply insensitivity can be achieved with either of two multiplexing methods. The first method places switches on the data inputs while the second places the switches on the analog bias voltages inherent to a current controlled inverter.

Abstract translation: 用于在数据输入之间复用的CMOS电路具有对电源噪声的高灵敏度，导致延迟变化。 通过利用多路复用器结构中的电流控制逆变器，可以通过两种复用方法之一实现电源不敏感。 第一种方法将开关置于数据输入端，而第二种方式将开关置于电流控制逆变器固有的模拟偏置电压上。