公开(公告)号：US07863918B2

公开(公告)日：2011-01-04

申请号：US11939145

申请日：2007-11-13

Applicant: Keith A. Jenkins ,  Seongwon Kim

Inventor： Keith A. Jenkins ,  Seongwon Kim

IPC: G01R31/02

CPC classification number: G01R31/2884 ,  H01L22/20 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.

Abstract translation: 用于对三维集成电路的集成电路层进行自检的装置和方法包括在具有待测试的第一电路的共同衬底上一体地形成一次性自检电路。 第一电路形成三维集成电路结构的层。 第一个电路使用自检电路的电路进行测试。 通过从第一电路分离自检电路来去除自检电路。

公开(公告)号：US20080195341A1

公开(公告)日：2008-08-14

申请号：US12105374

申请日：2008-04-18

Applicant: Keith A. Jenkins ,  Seongwon Kim

Inventor： Keith A. Jenkins ,  Seongwon Kim

IPC: G01R29/02

CPC classification number: G01R31/3016

Abstract: A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Abstract translation: 提供了一种用于确定组件的延迟时间间隔的系统和方法。 该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。 该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

公开(公告)号：US07378831B1

公开(公告)日：2008-05-27

申请号：US11624392

申请日：2007-01-18

Applicant: Keith A. Jenkins ,  Seongwon Kim

Inventor： Keith A. Jenkins ,  Seongwon Kim

IPC: G01R19/00 ,  G01R29/02 ,  H03H11/26

CPC classification number: G01R31/3016

Abstract: A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

Abstract translation: 提供了一种用于确定组件的延迟时间间隔的系统和方法。 该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。 该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

公开(公告)号：US20150303871A1

公开(公告)日：2015-10-22

申请号：US13569815

申请日：2012-08-08

Applicant: Keith A. Jenkins ,  Yu-ming Lin

Inventor： Keith A. Jenkins ,  Yu-ming Lin

IPC: H03B5/12 ,  H01L29/16 ,  H01L29/786

CPC classification number: H03B5/1228 ,  H01L29/1606 ,  H01L29/78684 ,  H03B5/1203 ,  H03B7/06 ,  H03B2200/0084

Abstract: An oscillator circuit includes a field effect transistor and a resonant circuit having a first terminal connected to the field effect transistor. The resonant circuit includes an inductance and a capacitance and has a second terminal for connecting to a radiator. The field effect transistor includes a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The graphene channel is disposed relative to the gate electrode for being biased by the gate electrode into a negative differential resistance region of operation. The oscillator circuit is capable of generating a continuous wave THz frequency signal, and is further capable of being enabled and disabled by the bias applied to the gate electrode.

Abstract translation: 振荡器电路包括场效应晶体管和具有连接到场效应晶体管的第一端子的谐振电路。 谐振电路包括电感和电容，并且具有用于连接到散热器的第二端子。 场效应晶体管包括耦合到栅极电压源的栅电极，源电极，漏电极和设置在源电极和漏电极之间并与其电连接的石墨烯通道。 石墨烯通道相对于栅电极设置，以便被栅电极偏压成负的差分电阻区域。 振荡器电路能够产生连续波THz频率信号，并且还能够通过施加到栅电极的偏置使能和禁止。

公开(公告)号：US08829922B2

公开(公告)日：2014-09-09

申请号：US13029214

申请日：2011-02-17

Applicant: Karthik Balakrishnan ,  Keith A. Jenkins

Inventor： Karthik Balakrishnan ,  Keith A. Jenkins

IPC: G01R27/28 ,  G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2621 ,  G01R31/2882

Abstract: An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

Abstract translation: 一种用于确定被测晶体管器件的交流（AC）延迟变化的装置包括环形振荡器，环形振荡器具有被配置在环形振荡器的反馈路径内的被测晶体管器件; 以及被配置为测量第一信号延迟路径和第二信号延迟路径之间的差的电路，所述第一信号延迟路径位于被测晶体管器件的栅极端子和漏极端子之间，并且所述第二信号延迟路径位于 源极端子和被测晶体管器件的漏极端子。

公开(公告)号：US20110235390A1

公开(公告)日：2011-09-29

申请号：US12729856

申请日：2010-03-23

Applicant: Tymon Barwicz ,  Keith A. Jenkins ,  Supratik Guha

Inventor： Tymon Barwicz ,  Keith A. Jenkins ,  Supratik Guha

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/404 ,  G11C13/0007 ,  H01L28/40 ,  H01L49/003

Abstract: A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation.

Abstract translation: 提供了一种存储器件及其形成方法。 存储器件包括衬底; 设置在基板上的一组电极; 形成在该组电极之间的电介质层; 以及形成在所述电极组之间的过渡金属氧化物层，所述过渡金属氧化物层被配置为经历金属 - 绝缘体转变（MIT）以执行读取或写入操作。

公开(公告)号：US07791330B2

公开(公告)日：2010-09-07

申请号：US12125730

申请日：2008-05-22

Applicant: David F. Heidel ,  Keith A. Jenkins

Inventor： David F. Heidel ,  Keith A. Jenkins

IPC: G01R13/02

CPC classification number: H04L1/205 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31709 ,  G01R31/31725

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract translation: 提供一种用于接收参考时钟和感兴趣信号的片上抖动测量电路和相应方法，该电路包括用于锁存和比较感兴趣信号到参考时钟的到达时间的锁存器，信号中的时钟计数器 与锁存器通信，用于对接收和锁存的参考时钟周期的数量进行计数;与参考时钟的信号通信的延迟链，用于改变参考时钟的到达时间;延迟链具有第一级，中间级和最后一位 以及与延迟链的至少一个中间级信号通信的电压控制器，用于控制参考时钟的到达时间的延迟，其中电压控制器控制延迟链的第一和最后阶段以保持 全电压摆幅独立于延时。

公开(公告)号：US07764080B2

公开(公告)日：2010-07-27

申请号：US12200334

申请日：2008-08-28

Applicant: Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

Inventor： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

IPC: G01R31/26

CPC classification number: G01R31/2621

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

Abstract translation: 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

公开(公告)号：US20090309625A1

公开(公告)日：2009-12-17

申请号：US12542184

申请日：2009-08-17

Applicant: Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

Inventor： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

IPC: G01R31/26

CPC classification number: G01R31/2621

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

Abstract translation: 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

公开(公告)号：US07439724B2

公开(公告)日：2008-10-21

申请号：US10638825

申请日：2003-08-11

Applicant: David F. Heidel ,  Keith A. Jenkins

Inventor： David F. Heidel ,  Keith A. Jenkins

IPC: G01R23/00 ,  H04L7/00 ,  H03L7/06

CPC classification number: H04L1/205 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31709 ,  G01R31/31725

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract translation: 提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链 用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟 的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。