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    Method of manufacturing TFT and array TFT
    41.
    发明申请
    Method of manufacturing TFT and array TFT 有权
    制造TFT和阵列TFT的方法

    公开(公告)号：US20110183478A1

    公开(公告)日：2011-07-28

    申请号：US12923051

    申请日：2010-08-31

    Applicant: Jae-woo CHUNG ,  Seung-ho LEE ,  Young-ki HONG ,  Sung-gyu KANG ,  Joong-hyuk KIM

    Inventor： Jae-woo CHUNG ,  Seung-ho LEE ,  Young-ki HONG ,  Sung-gyu KANG ,  Joong-hyuk KIM

    IPC: H01L21/336

    CPC classification number: H01L21/28008 ,  H01L27/1285 ,  H01L27/1292

    Abstract: A method of manufacturing a thin film transistor includes sequentially forming a gate and at least one insulation layer on a substrate, forming a source electrode and a drain electrode on the at least one insulation layer, and forming a channel layer formed of a semiconductor on a part of the source electrode and the drain electrode, wherein the gate, the source electrode, and the drain electrode are formed by using a hybrid inkjet printing apparatus.

    Abstract translation: 制造薄膜晶体管的方法包括在基板上依次形成栅极和至少一个绝缘层，在至少一个绝缘层上形成源电极和漏电极，以及在半导体层上形成沟道层 源电极和漏电极的一部分，其中栅极，源电极和漏电极通过使用混合喷墨打印装置形成。

    Gas Distribution Apparatus and Substrate Processing Apparatus Having the Same
    42.
    发明申请
    Gas Distribution Apparatus and Substrate Processing Apparatus Having the Same 审中-公开
    气体分配装置和具有相同功能的基板处理装置

    公开(公告)号：US20110048325A1

    公开(公告)日：2011-03-03

    申请号：US12746505

    申请日：2010-02-26

    Applicant: Sun Hong Choi ,  Seung Ho Lee ,  Young Hee Lee

    Inventor： Sun Hong Choi ,  Seung Ho Lee ,  Young Hee Lee

    IPC: C23C16/455 ,  C23C16/458

    CPC classification number: C23C16/45565 ,  C23C16/452 ,  C23C16/45574 ,  C23C16/45591

    Abstract: Provided are a gas distribution apparatus and a substrate treating apparatus including the same. The substrate treating apparatus includes a chamber comprising a reaction space, a substrate seat unit disposed in the reaction space of the chamber to radially seat a plurality of substrates with respect to a center thereof, and a gas distribution device comprising a first gas distribution part configured to eject at least two source materials onto a substrate through routes different from each other and a second gas distribution part configured to eject a source material having a decomposition temperature greater than an average of decomposition temperatures of the at least two source materials onto the substrate. The first gas distribution part is divided into at least two sections and disposed such that the second gas distribution part is positioned therebetween; and couplable and separable to/from one another.

    Abstract translation: 提供一种气体分配装置和包括该气体分配装置的基板处理装置。 基板处理装置包括：室，包括反应空间;基板座单元，设置在所述室的反作用空间中，以相对于其中心径向安置多个基板;以及气体分配装置，包括：第一气体分配部， 通过彼此不同的路线将至少两种源材料喷射到基板上;以及第二气体分配部件，其配置成将具有大于所述至少两种源材料的分解温度的平均分解温度的源材料喷射到所述基板上。 第一气体分配部分被分成至少两个部分并且被布置成使得第二气体分配部分位于它们之间; 并且可以彼此联接和分离。

    Flat lamp device with multi electron source array
    45.
    发明授权
    Flat lamp device with multi electron source array 失效
    具有多电子源阵列的扁平灯装置

    公开(公告)号：US07446469B2

    公开(公告)日：2008-11-04

    申请号：US11201652

    申请日：2005-08-10

    Applicant: Seung-Ho Lee

    Inventor： Seung-Ho Lee

    IPC: H01J1/62 ,  H01J63/04

    CPC classification number: H01J63/02 ,  H01J63/06

    Abstract: A flat lamp device includes lower and upper glass plates facing each other in parallel; spacers interposed between the plates to keep a distance therebetween; a cathode electrode singly formed over the entire upper surface of the lower glass plate; an insulation film formed on the cathode electrode; semiconductor films independently patterned on the insulation at intervals; a catalyst metal layer laminated on a buffer metal layer to improve adhesive force of the catalyst metal formed on the semiconductor films; carbon nano-tubes formed on the catalyst metal layer; a grid electrode installed above the carbon nano-tubes between the plates to guide electron emission from the carbon nano-tubes with a mesh shape having an opening for passage of the emitted electrons; an anode electrode formed below the upper glass plate to accelerate the emitted electrons; and a fluorescent layer formed on a lower surface of the anode electrode.

    Abstract translation: 平板灯装置包括并列的彼此相对的下玻璃板和上玻璃板; 插入板之间的间隔件以保持它们之间的距离; 单独形成在下玻璃板的整个上表面上的阴极电极; 形成在阴极上的绝缘膜; 半导体膜间隔独立地在绝缘层上图案化; 层叠在缓冲金属层上的催化剂金属层，以改善形成在半导体膜上的催化剂金属的粘附力; 形成在催化剂金属层上的碳纳米管; 栅格电极安装在板之间的碳纳米管上方，以引导具有网孔形状的碳纳米管的电子发射，该网状形状具有用于发射电子通过的开口; 形成在上玻璃板下面以加速发射的电子的阳极电极; 以及形成在阳极电极的下表面上的荧光层。

    Flat lamp device with multi electron source array
    46.
    发明申请
    Flat lamp device with multi electron source array 失效
    具有多电子源阵列的扁平灯装置

    公开(公告)号：US20060244357A1

    公开(公告)日：2006-11-02

    申请号：US11201652

    申请日：2005-08-10

    Applicant: Seung-Ho Lee

    Inventor： Seung-Ho Lee

    IPC: H01J1/62

    CPC classification number: H01J63/02 ,  H01J63/06

    Abstract: Disclosed is a flat lamp device, including lower and upper glass plates facing each other in parallel; spacers interposed between the plates to keep distance therebetween; a cathode electrode singly formed over the entire upper surface of the lower glass plate; an insulation film formed on the cathode electrode; semiconductor films independently patterned on the insulation film at intervals; a catalyst-metal layer laminated on the buffer metal to improve the adhesion of catalyst metal formed on the semiconductor films; carbon nano-tubes formed on the catalyst-metal layer; a grid electrode installed on the carbon nano-tubes between the plates to guide electron emission from the carbon nano-tubes with a mesh shape having an opening for passage of the emitted electrons; an anode electrode formed below the upper glass plate to accelerate the emitted electrons; and a fluorescent layer formed below the anode electrode to emit light by collision with the accelerated electrons.

    Abstract translation: 公开了一种扁平灯装置，包括并列相对的下玻璃板和上玻璃板; 插入板之间的间隔件以保持它们之间的距离; 单独形成在下玻璃板的整个上表面上的阴极电极; 形成在阴极上的绝缘膜; 间隔地在绝缘膜上独立构图的半导体膜; 层叠在缓冲金属上的催化剂 - 金属层，以改善形成在半导体膜上的催化剂金属的粘附性; 形成在催化剂 - 金属层上的碳纳米管; 安装在板之间的碳纳米管上的栅极，以引导具有网孔形状的碳纳米管的电子发射，该网状形状具有用于发射电子通过的开口; 形成在上玻璃板下面以加速发射的电子的阳极电极; 以及形成在阳极电极下方的荧光层，通过与加速电子的碰撞而发光。

    Semiconductor device isolation structure and fabrication method of semiconductor device using the same
    48.
    发明授权
    Semiconductor device isolation structure and fabrication method of semiconductor device using the same 失效
    半导体器件隔离结构及使用其的半导体器件的制造方法

    公开(公告)号：US06214657B1

    公开(公告)日：2001-04-10

    申请号：US09083438

    申请日：1998-05-22

    Applicant: Seung Ho Lee

    Inventor： Seung Ho Lee

    IPC: H01L218238

    CPC classification number: H01L21/823481 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283

    Abstract: A semiconductor device isolation structure includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, and an isolation layer formed in the field region of the substrate deeper than the buried insulation layer. A method for isolating a semiconductor device includes the steps of preparing a semiconductor substrate, defining an active region and a field region in the substrate, forming an insulation layer buried in the active region of the substrate, and forming an isolation layer in the field region of the substrate to be deeper than the buried insulation layer. The invention applies to an SOI (Silicon On Insulator) provided with a SIMOX (Separation by Implanted Oxygen) type, for effectively overcoming interfacial defects between a buried oxide film and a semiconductor substrate, and improves a reliability of the semiconductor device by planarizing the same.

    Abstract translation: 半导体器件隔离结构包括：包括有源区和场区的半导体衬底，埋在衬底的有源区中的绝缘层，以及形成在比掩埋绝缘层更深的衬底的场区中的隔离层。 一种用于隔离半导体器件的方法包括以下步骤：制备半导体衬底，在衬底中限定有源区和场区，形成掩埋在衬底的有源区中的绝缘层，以及在场区中形成隔离层 的衬底比掩埋绝缘层更深。 本发明适用于具有SIMOX（通过注入氧分离）型的SOI（绝缘体上硅），用于有效地克服掩埋氧化膜和半导体衬底之间的界面缺陷，并且通过使其平坦化来提高半导体器件的可靠性 。

    Method of isolating semiconductor devices
    49.
    发明授权
    Method of isolating semiconductor devices 有权
    隔离半导体器件的方法

    公开(公告)号：US6140207A

    公开(公告)日：2000-10-31

    申请号：US146750

    申请日：1998-09-04

    Applicant: Seung-Ho Lee

    Inventor： Seung-Ho Lee

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76229

    Abstract: The present invention relates to a method of isolating semiconductor devices enabling to prevent an active area from being reduced due to the increase of an isolation area by means of forming trenches, and includes the steps of forming a mask on a semiconductor substrate wherein the mask discloses field areas, forming a first and second trench in the field areas of the semiconductor substrate wherein the first trench has a larger size and a lower aspect ratio than those of the second trench and wherein the second trench has a smaller size and a higher aspect ratio than those of the first trench, depositing filling oxide on the mask and in the first and second trench by a method including characteristic of sputtering wherein the first and second trench are filled up with the filling oxide and a void is formed on a lower part of the second trench, and forming field oxide film by means of etching back the filling oxide to remain inside the first and second trench.

    Abstract translation: 本发明涉及一种隔离半导体器件的方法，其能够通过形成沟槽来防止由于隔离区域的增加而导致的有源区域的减小，并且包括在半导体衬底上形成掩模的步骤，其中掩模公开 场区域，在半导体衬底的场区域中形成第一和第二沟槽，其中第一沟槽具有比第二沟槽更大的尺寸和更低的纵横比，并且其中第二沟槽具有较小的尺寸和较高的纵​​横比 通过包括溅射特性的方法在掩模和第一和第二沟槽中沉积填充氧化物，其中第一和第二沟槽填充有填充氧化物，并且在下部形成空隙 并且通过蚀刻回填充氧化物形成场氧化膜以保持在第一和第二沟槽内。

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