公开(公告)号：US20130031330A1

公开(公告)日：2013-01-31

申请号：US13560414

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/10

CPC classification number: G06F13/1657 ,  G06F13/14 ,  G06F13/385

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract translation: 一种第一装置，包括被配置为从第二装置接收具有地址的存储器事务的第一接口; 第二个接口; 地址转换器，被配置为基于所述地址确定所述交易是否用于所述第一布置，如果是，则转换所述地址，或者如果所述交易是用于第三种布置以将所述交易转发到所述第二接口的所述地址， 接口被配置为将所述交易传送到所述第三装置，而不改变所述地址。

公开(公告)号：US20110135046A1

公开(公告)日：2011-06-09

申请号：US12959005

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H04L7/00

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 在所述第一和第二模具中的至少一个上提供同步器。 同步器被配置为使得任何未发送的控制信号值跨接口传输。

公开(公告)号：US20110133826A1

公开(公告)日：2011-06-09

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H01L25/00

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。

公开(公告)号：US07774574B2

公开(公告)日：2010-08-10

申请号：US10621012

申请日：2003-07-15

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F12/06

CPC classification number: G06F12/0292

Abstract: A prototype system having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract translation: 具有集成电路的原型系统，该集成电路包括片上处理器和通过接口连接到片外资源的片上路由器。 芯片上的请求引导单元接收存储器访问请求，并根据两个地址映射中的任一个引导它们。 在一个地址映射中，将第一范围的地址分配给至少一个片上资源，并且将第二范围的地址分配给该接口。 在另一个存储器地址映射中，第一个地址范围也被分配给接口。 还描述了包括这种请求引导单元的集成电路以及用于评估原型系统的方法。

公开(公告)号：US20090132749A1

公开(公告)日：2009-05-21

申请号：US12284329

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory.

Abstract translation: 公开了用于将数据预取入高速缓冲存储器系统的系统和方法。 这些系统和方法包括从系统存储器检索数据的一部分并且将检索到的数据部分的副本存储在高速缓冲存储器中。 这些系统和方法还包括监视已经被放置到预取存储器中的数据。

公开(公告)号：US20070283140A1

公开(公告)日：2007-12-06

申请号：US11787227

申请日：2007-04-13

Applicant: Andrew Jones ,  Stuart Ryan

Inventor： Andrew Jones ,  Stuart Ryan

IPC: G06F12/14 ,  G06F9/24

CPC classification number: G06F9/4403 ,  G06F21/575 ,  G06F2221/2105

Abstract: An integrated circuit is operable to execute boot loader code and a boot code from external memory. To provide security so that the CPU does not execute malicious codes, the circuit resets in a restricted mode in which only certain functional units may be connected. In the restricted mode the CPU is only able to fetch boot code from an external memory for transfer to an internal memory. A hash function operates on the fetched boot code to determine whether it is authentic and, if it is determined that the code is authentic the circuit is reset to an unrestricted mode to continue executing from the boot code now stored in the internal memory. Further security is provided by a watchdog timer function which resets the circuit if the boot code is not determined to be authentic within a threshold period of time.

Abstract translation: 集成电路可操作以从外部存储器执行引导加载器代码和引导代码。 为了提供安全性以使CPU不执行恶意代码，该电路在仅可以连接某些功能单元的限制模式下复位。 在限制模式下，CPU只能从外部存储器获取引导代码，以传输到内部存储器。 哈希函数对获取的引导代码进行操作以确定其是否是真实的，并且如果确定代码是可信的，则电路被重置为不受限制的模式以从现在存储在内部存储器中的引导代码继续执行。 看门狗定时器功能还提供进一步的安全性，如果在阈值时间段内引导代码未被确定为可靠的，则复位电路。