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    Boost converter having multiple outputs and method of operation thereof
    41.
    发明授权
    Boost converter having multiple outputs and method of operation thereof 失效
    具有多个输出的升压转换器及其操作方法

    公开(公告)号：US5847949A

    公开(公告)日：1998-12-08

    申请号：US946429

    申请日：1997-10-07

    Applicant: Yimin Jiang

    Inventor： Yimin Jiang

    IPC: H02M3/335 ,  H02M7/08

    CPC classification number: H02M3/33561 ,  Y10T307/707

    Abstract: A boost converter for converting an input voltage received at an input thereof into first and second output voltages provided at first and second outputs thereof, respectively, a method of power conversion and a power converter employing the boost converter or the method. In one embodiment, the boost converter includes: (1) a first switching circuit coupled to a first rail of the input and having a first switch and a first capacitor coupled in parallel, (2) a second switching circuit coupled to a second rail of the input and having a second switch and a second capacitor coupled in parallel and (3) a boost inductor, coupled in series between the first switching circuit and the second switching circuit, that provides a conductive path for the input DC voltage to flow serially through the first switching circuit and the second switching circuit to charge the first and second capacitors, respectively.

    Abstract translation: 一种升压转换器，用于将其输入处接收的输入电压分别转换为在其第一和第二输出处提供的第一和第二输出电压，电力转换方法和采用升压转换器的方法的功率转换器。 在一个实施例中，升压转换器包括：（1）耦合到输入的第一导轨的第一开关电路，并具有并联耦合的第一开关和第一电容器，（2）耦合到第二开关 输入并具有并联耦合的第二开关和第二电容器，以及串联耦合在第一开关电路和第二开关电路之间的升压电感器，其提供用于输入DC电压串行流过的导电路径 第一开关电路和第二开关电路分别对第一和第二电容器充电。

    Split-boost circuit having imbalance protection circuitry
    42.
    发明授权
    Split-boost circuit having imbalance protection circuitry 失效
    分压升压电路具有不平衡保护电路

    公开(公告)号：US5689410A

    公开(公告)日：1997-11-18

    申请号：US668173

    申请日：1996-06-21

    Applicant: Yimin Jiang

    Inventor： Yimin Jiang

    IPC: H02M3/158 ,  H05B37/02

    CPC classification number: H02M3/158 ,  H02M2001/009

    Abstract: A rectifier architecture with a split boost circuit having protection circuitry for protecting circuit elements of the split boost. The split boost includes a voltage input terminal, an inductor, two voltage output terminals, a boost diode and branches A and B. Each branch A and B, includes: a switch, a protection circuit, and a capacitor. In a preferred embodiment, the protection circuit is a parallel resistor-diode pair coupled between the capacitor and the switch. The purpose of the protection circuit is to limit circulating current between capacitors when switches in branches A and B are active.

    Abstract translation: 具有分离升压电路的整流器结构，其具有用于保护分流升压的电路元件的保护电路。 分流升压包括电压输入端子，电感器，两个电压输出端子，升压二极管和分支A和B.每个分支A和B包括：开关，保护电路和电容器。 在优选实施例中，保护电路是耦合在电容器和开关之间的并联电阻 - 二极管对。 保护电路的目的是限制分支A和B中的开关处于活动状态时电容器之间的循环电流。

    Friction-welded structure assembly, water-cooled internal combustion engine cylinder head, water-cooled internal combustion engine and machine equipped with same
    43.
    发明授权
    Friction-welded structure assembly, water-cooled internal combustion engine cylinder head, water-cooled internal combustion engine and machine equipped with same 有权

    公开(公告)号：US10197006B2

    公开(公告)日：2019-02-05

    申请号：US15028692

    申请日：2014-12-22

    Applicant: Shanghai Jiaotong University ,  Yimin Jiang ,  Yaofu Jiang

    Inventor： Yaofu Jiang ,  Wenjiang Ding ,  Liming Peng ,  Penghuai Fu ,  Yongkui Zhu

    IPC: B23K20/12 ,  F02F1/36 ,  F02F1/24 ,  F02F1/42 ,  H05B6/02 ,  F01L3/08 ,  B23K101/00

    Abstract: The invention provides a friction-welded structure assembly, comprising a first workpiece (10B), a second workpiece (10C) and a friction welding connecting part (10A). The lower side of the friction welding connecting part (10A) has a first friction welding junction interface (10H) which is in contact with a surface of the first workpiece (10B) and a second friction welding junction interface (11H) which is in contact with a surface of the second workpiece (10C). The friction welding connecting part (10A) is tightly pressed on both the first workpiece (10B) and the second workpiece (10C) which are positioned to be relatively corresponding and fixed to each other, while being moved under a pressure, so as to heat said first friction welding junction interface (10H) and said second friction welding junction interface (11H), then said friction welding connecting part (10A) is stopped under the pressure, and said first friction welding junction interface (10H) and said second friction welding junction interface (11H) become cool, thereby said first workpiece (10B) and said second workpiece (10C) are welded together to form the friction-welded structure assembly via said friction welding connecting part (10A). Also, The invention relates to a water-cooled internal combustion engine cylinder head using the friction-welded structure assembly described above.

    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK)
    46.
    发明授权
    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK) 有权
    用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，

    公开(公告)号：US08199847B2

    公开(公告)日：2012-06-12

    申请号：US11879607

    申请日：2007-07-18

    Applicant: Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    Inventor： Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    IPC: H03C5/00 ,  H03D5/00 ,  H03K7/10 ,  H03K9/10

    CPC classification number: H04L27/3488 ,  H04L27/183

    Abstract: A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.

    Abstract translation: 提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。 本发明包括耦合到第一位流的定时误差累加器。 第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。 相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。 相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。 还提供耦合到相位和定时误差补偿器的较高阶调制器。 高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK)
    49.
    发明授权
    Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK) 有权
    用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，

    公开(公告)号：US07260159B2

    公开(公告)日：2007-08-21

    申请号：US10142703

    申请日：2002-05-10

    Applicant: Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    Inventor： Lin-Nan Lee ,  Feng-Wen Sun ,  Mustafa Eroz ,  Yimin Jiang

    IPC: H03D3/22 ,  H04L27/22

    CPC classification number: H04L27/3488 ,  H04L27/183

    Abstract: A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.

    Abstract translation: 提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。 本发明包括耦合到第一位流的定时误差累加器。 第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。 相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。 相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。 还提供耦合到相位和定时误差补偿器的高阶调制器。 高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

    Power converter including circuits for improved operational control of synchronous rectifiers therein
    50.
    发明授权
    Power converter including circuits for improved operational control of synchronous rectifiers therein 有权
    电力转换器包括用于改善其中同步整流器的运行控制的电路

    公开(公告)号：US06674658B2

    公开(公告)日：2004-01-06

    申请号：US10062639

    申请日：2002-02-01

    Applicant: Hengchun Mao ,  Yimin Jiang

    Inventor： Hengchun Mao ,  Yimin Jiang

    IPC: H02M3335

    CPC classification number: H02M3/33592 ,  Y02B70/1475

    Abstract: A power converter device using synchronous rectifiers and method for controlling operation thereof are provided. A first synchronous rectifier is coupled to the secondary transformer winding to pass a voltage induced at the secondary winding in response to an input voltage supplied to the primary transformer winding during an on-state of a main power switch. A first drive circuit is coupled to the gate terminal of the first synchronous rectifier to selectively activate and deactivate the first rectifier in correspondence with the respective on and off states of the main power switch based on a gate voltage supplied by the first drive circuit, with at least one circuit parameter being selected in the first drive circuit for maintaining the gate voltage within a predefined range regardless of variation in the level of the input voltage.

    Abstract translation: 提供了一种使用同步整流器的电力转换装置及其控制方法。 第一同步整流器耦合到次级变压器绕组，以响应于在主电源开关的导通状态期间提供给初级变压器绕组的输入电压，传递在次级绕组处感应的电压。 第一驱动电路耦合到第一同步整流器的栅极端子，以基于由第一驱动电路提供的栅极电压与主电源开关的各自的导通和关断状态对应地选择性地激活和去激活第一整流器， 在第一驱动电路中选择至少一个电路参数，用于将栅极电压维持在预定范围内，而与输入电压电平的变化无关。

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