公开(公告)号：US11847048B2

公开(公告)日：2023-12-19

申请号：US17031518

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F12/02 ,  G06F12/0815 ,  G06F15/173 ,  G06F12/0868 ,  G06F12/084

CPC classification number: G06F12/0238 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0868 ,  G06F15/17331

Abstract: A processing device and methods of controlling remote persistent writes are provided. Methods include receiving an instruction of a program to issue a persistent write to remote memory. The methods also include logging an entry in a local domain when the persistent write instruction is received and providing a first indication that the persistent write will be persisted to the remote memory. The methods also include executing the persistent write to the remote memory and providing a second indication that the persistent write to the remote memory is completed. The methods also include providing the first and second indications when it is determined not to execute the persistent write according to global ordering and providing the second indication without providing the first indication when it is determined to execute the persistent write to remote memory according to global ordering.

公开(公告)号：US20230359558A1

公开(公告)日：2023-11-09

申请号：US17739817

申请日：2022-05-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Mohamed Assem Abd ElMohsen Ibrahim

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F2212/251

Abstract: An approach is provided for skipping, i.e., not processing and/or deleting, near-memory processing commands when one or more skip criteria are satisfied. Examples of skip criteria include, without limitation, specific operations, specific operands, and combinations of specific operations and specific operands. The approach is implemented at one or more memory command processing elements in the memory pipeline of a processor, such as memory controllers, caches, queues, and buffers, etc. Implementations include exceptions to skipping in certain situations and software support for configuring skip criteria, including particular operations and operands for which skip checking is performed. The approach provides the benefits of reducing command bus traffic and power consumption while maintaining functional correctness.

公开(公告)号：US11797201B2

公开(公告)日：2023-10-24

申请号：US17745278

申请日：2022-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0607

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

公开(公告)号：US20230098421A1

公开(公告)日：2023-03-30

申请号：US17490703

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Mohamed Assem Abd ElMohsen Ibrahim ,  Shaizeen Aga

IPC: G06F17/17 ,  G06F7/483

Abstract: Methods and apparatuses include a processing unit which helps control the speed and computational resources required for arithmetic operations of two numbers in a first format. The control unit of the processing unit approximates the arithmetic operations using a plurality of decomposed numbers in a second format that facilitates faster calculations than the first format, such that performing arithmetic operations using the decomposed numbers is capable of approximating the results of the arithmetic operations of the two numbers in the first format.

公开(公告)号：US20230065546A1

公开(公告)日：2023-03-02

申请号：US17489576

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Abd ElMohsen Ibrahim ,  Onur Kayiran ,  Shaizeen Aga

IPC: G06F16/2457

Abstract: An electronic device includes a plurality of nodes, each node having a processor that performs operations for processing instances of input data through a model, a local memory that stores a separate portion of model data for the model, and a controller. The controller identifies model data that meets one or more predetermined conditions in the separate portion of the model data in the local memory in some or all of the nodes that is accessible by the processors when processing the instances of input data through the model. The controller then copies the model data that meets the one or more predetermined conditions from the separate portion of the model data in the local memory in the some or all of the nodes to local memories in other nodes. In this way, the controller distributes model data that meets the one or more predetermined conditions among the nodes, making the model data that meets the one or more predetermined conditions available to the nodes without performing remote memory accesses.

公开(公告)号：US20230004491A1

公开(公告)日：2023-01-05

申请号：US17364854

申请日：2021-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/02

Abstract: A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.

公开(公告)号：US20220206899A1

公开(公告)日：2022-06-30

申请号：US17133843

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Nuwan Jayasena ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Shrikanth Ganapathy

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.

公开(公告)号：US20220206839A1

公开(公告)日：2022-06-30

申请号：US17135381

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F9/48 ,  G06F3/06

Abstract: An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.

公开(公告)号：US20220066662A1

公开(公告)日：2022-03-03

申请号：US17006646

申请日：2020-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

IPC: G06F3/06

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

公开(公告)号：US20210373805A1

公开(公告)日：2021-12-02

申请号：US16885677

申请日：2020-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06

Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.