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    Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness
    43.
    发明授权
    Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness 失效
    采用冗余电路系统补偿缺陷的半导体存储器集成电路

    公开(公告)号：US06490210B2

    公开(公告)日：2002-12-03

    申请号：US09867796

    申请日：2001-05-31

    申请人： Satoru Takase ,  Takeshi Nagai

    发明人： Satoru Takase ,  Takeshi Nagai

    IPC分类号： G11C700

    CPC分类号： G11C29/14 ,  G11C11/401 ,  G11C29/50

    摘要： A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a memory cell array having a plurality of normal signal lines for selecting a memory cell, a redundant cell array including three or more of odd number of spare signal lines for compensating for defectiveness in the memory cell array, a decoder for decoding an address signal to select a normal signal line, a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line, and a test control circuit for controlling the decoder and the spare decoder to perform a test of applying voltage between adjacent signal lines in the normal signal lines and the spare signal lines. The test control circuit sets electric potential levels in a signal line group including the normal signal lines and the spare signal lines so that at the time of a test, electric potential levels of adjacent signal lines are opposite to each other.

    摘要翻译： 提供一种半导体存储器集成电路，其能够同时向正常信号线和备用信号线施加电压应力，从而减少进行测试所需的时间。 半导体存储器集成电路包括具有用于选择存储单元的多条正常信号线的存储单元阵列，包括用于补偿存储单元阵列中的缺陷的奇数个备用信号线的三个或更多个的冗余单元阵列，解码器 用于解码地址信号以选择正常信号线;当输入缺陷地址信号时激活的备用解码器，用于解码缺陷地址信号以选择备用信号线;以及测试控制电路，用于控制解码器和 备用解码器执行在正常信号线和备用信号线之间的相邻信号线之间施加电压的测试。 测试控制电路设置包括正常信号线和备用信号线的信号线组中的电位电平，使得在测试时，相邻信号线的电位电平彼此相反。

    Redundancy circuit of semiconductor memory
    44.
    发明授权
    Redundancy circuit of semiconductor memory 失效
    半导体存储器的冗余电路

    公开(公告)号：US06392937B2

    公开(公告)日：2002-05-21

    申请号：US09861843

    申请日：2001-05-22

    申请人： Takeshi Nagai

    发明人： Takeshi Nagai

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/812

    摘要： A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank.

    摘要翻译： 半导体具有可以同时访问的八个存储体。 在每个银行内，都有两个固定的备用行解码器和两个映射备用行解码器。 在每个存储体内，相应于固定的备用排解码器​​提供两个固定熔丝组。 例如，在每个存储体的外部提供八个映射熔丝组，与映射备用行解码器没有关联。 每个映射熔丝组存储用于确定映射熔丝组与特定存储体内的特定映射备用行解码器的对应关系的映射数据。

    Moving picture coding and/or decoding systems, and variable-length coding and/or decoding system
    45.
    发明授权
    Moving picture coding and/or decoding systems, and variable-length coding and/or decoding system 失效
    运动图像编码和/或解码系统以及可变长度编码和/或解码系统

    公开(公告)号：US06317461B1

    公开(公告)日：2001-11-13

    申请号：US09476117

    申请日：2000-01-03

    申请人： Takeshi Chujoh ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

    发明人： Takeshi Chujoh ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

    IPC分类号： H04N718

    CPC分类号： H04N19/69 ,  H04N19/152 ,  H04N19/159 ,  H04N19/176 ,  H04N19/187 ,  H04N19/37 ,  H04N19/46 ,  H04N19/52 ,  H04N19/61 ,  H04N19/65 ,  H04N19/66 ,  H04N19/70 ,  H04N19/89 ,  H04N19/93

    摘要： A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

    摘要翻译： 编码和/或解码系统包括：码字表，用于在其中存储多个码字，其能够在前向和后向被解码，并且形成为使得码字的分隔符能够被 由代码字的预定权重识别，使得码字对应于不同的源符号; 编码器，用于从码字表中选择与输入的源符号对应的码字; 以及同步间隔设定部分，用于使用由编码器选择的代码字，每隔预定间隔准备编码数据，并用于插入能够沿向后方向解码的填充码。 因此，可以减少无用的位模式，通过更少的计算和存储量来提高编码效率，并且即使在使用填充位的每个间隔设置同步间隔的情况下，也可以在正向和反向方向上解码可变长度代码。

    Video encoding and decoding apparatus
    47.
    发明授权
    Video encoding and decoding apparatus 失效
    视频编解码装置

    公开(公告)号：US06188792B1

    公开(公告)日：2001-02-13

    申请号：US09382770

    申请日：1999-08-25

    申请人： Takeshi Chujoh ,  Takeshi Nagai ,  Yoshihiro Kikuchi ,  Kenshi Dachiku

    发明人： Takeshi Chujoh ,  Takeshi Nagai ,  Yoshihiro Kikuchi ,  Kenshi Dachiku

    IPC分类号： G06K936

    CPC分类号： H04N19/587 ,  H04N19/107 ,  H04N19/132 ,  H04N19/137 ,  H04N19/146 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152 ,  H04N19/166 ,  H04N19/17 ,  H04N19/174 ,  H04N19/176 ,  H04N19/44 ,  H04N19/527 ,  H04N19/61

    摘要： An encoding apparatus comprising a encoder for encoding an input video signal, thereby generating encoded data, an output buffer for receiving the encoded data and outputting the data at a predetermined transmission rate, and an encoding control circuit for selecting a frame to be encoded. In the encoding control circuit, the target number of bits for each frame is calculated on the basis of the encoding bit rate, the encoding frame rate and the limits of delay, all of which are set externally. The number of encoded bits, thus calculated, is compared with the target number of encoded bits. A quantizer and a switch are controlled in accordance with the difference between the number of encoded code and the target number of encoded bits, thereby adjusting a quantization parameter and the number of frames which are to be skipped.

    摘要翻译： 一种编码装置，包括用于编码输入视频信号的编码器，从而产生编码数据，用于接收编码数据并以预定传输速率输出数据的输出缓冲器，以及用于选择要编码的帧的编码控制电路。 在编码控制电路中，根据编码比特率，编码帧率和延迟限制来计算每帧的目标比特数，所有这些都是从外部设置的。 将如此计算的编码比特数与编码比特的目标数进行比较。 根据编码代码的数量与目标编码比特数之间的差来控制量化器和开关，从而调整量化参数和要跳过的帧数。

    Video encoding and decoding apparatus
    49.
    发明授权
    Video encoding and decoding apparatus 失效
    视频编解码装置

    公开(公告)号：US6002802A

    公开(公告)日：1999-12-14

    申请号：US736240

    申请日：1996-10-24

    申请人： Takeshi Chujoh ,  Takeshi Nagai ,  Yoshihiro Kikuchi ,  Kenshi Dachiku

    发明人： Takeshi Chujoh ,  Takeshi Nagai ,  Yoshihiro Kikuchi ,  Kenshi Dachiku

    IPC分类号： G06T9/00 ,  H04N19/89 ,  G06K9/34

    CPC分类号： H04N19/587 ,  H04N19/107 ,  H04N19/132 ,  H04N19/137 ,  H04N19/166 ,  H04N19/17 ,  H04N19/174 ,  H04N19/176 ,  H04N19/44 ,  H04N19/527 ,  H04N19/61 ,  H04N19/146 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152

    摘要： An encoding apparatus comprising a encoder for encoding an input video signal, thereby generating encoded data, an output buffer for receiving the encoded data and outputting the data at a predetermined transmission rate, and an encoding control circuit for selecting a frame to be encoded. In the encoding control circuit, the target number of bits for each frame is calculated on the basis of the encoding bit rate, the encoding frame rate and the limits of delay, all of which are set externally. The number of encoded bits, thus calculated, is compared with the target number of encoded bits. A quantizer and a switch are controlled in accordance with the difference between the number of encoded code and the target number of encoded bits, thereby adjusting a quantization parameter and the number of frames which are to be skipped.

    摘要翻译： 一种编码装置，包括用于编码输入视频信号的编码器，从而产生编码数据，用于接收编码数据并以预定传输速率输出数据的输出缓冲器，以及用于选择要编码的帧的编码控制电路。 在编码控制电路中，根据编码比特率，编码帧率和延迟限制来计算每帧的目标比特数，所有这些都是从外部设置的。 将如此计算的编码比特数与编码比特的目标数进行比较。 根据编码代码的数量与目标编码比特数之间的差来控制量化器和开关，从而调整量化参数和要跳过的帧数。