-
公开(公告)号：US4473803A
公开(公告)日：1984-09-25
申请号：US438939
申请日：1982-11-03
摘要： An electronic volume for effecting a control of an impedance circuit in audio devices or the like includes a variable impedance circuit disposed in a signal transmission path and adapted to vary the impedance in accordance with an electronic control signal. A hold/through gate switchable between a hold state and a through state and adapted to permit, when taking the through state, the input signal to pass therethrough in synchronization with a clock signal of a predetermined period and, when taking the hold state, to hold and deliver the input signal as a control signal to the variable impedance circuit, is connected to a control circuit adapted to vary the input signal supplied to the hold/through gate at a predetermined rate at each time of receipt of the hold/through gate, and a rate changing means is provided for changing the rate of variation of the input signal coming through the hold/through gate.
摘要翻译： 用于实现音频装置等中的阻抗电路的控制的电子音量包括设置在信号传输路径中并适于根据电子控制信号改变阻抗的可变阻抗电路。 保持/通过门可在保持状态和通过状态之间切换，并且适于在通过状态时允许输入信号与预定时段的时钟信号同步地通过，并且当采取保持状态时，保持/ 保持并将输入信号作为控制信号传送到可变阻抗电路，连接到控制电路，该控制电路适于在每次接收到保持/通过时通过预定速率改变提供给保持/通过门的输入信号 并且提供速率改变装置，用于改变通过保持/通过门的输入信号的变化率。
-
公开(公告)号：US08338889B2
公开(公告)日：2012-12-25
申请号：US13137920
申请日：2011-09-21
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。
-
公开(公告)号：US20120012935A1
公开(公告)日：2012-01-19
申请号：US13137920
申请日：2011-09-21
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
-
公开(公告)号：US20100304555A1
公开(公告)日：2010-12-02
申请号：US12805533
申请日：2010-08-04
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。
-
公开(公告)号：US20070190708A1
公开(公告)日：2007-08-16
申请号：US11700147
申请日：2007-01-31
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。
-
公开(公告)号：US20060275988A1
公开(公告)日：2006-12-07
申请号：US11404772
申请日：2006-04-17
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译： 根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。
-
公开(公告)号：US4689445A
公开(公告)日：1987-08-25
申请号：US796777
申请日：1985-11-12
申请人： Shoji Seike , Takao Totoki , Akio Kaneko
发明人： Shoji Seike , Takao Totoki , Akio Kaneko
IPC分类号： H01B17/02
CPC分类号： H01B17/02
摘要： A porcelain electrical insulator resistant to destruction by projectiles comprises a shed and a head portion protrusively and integrally formed with the shed. The thinnest part of the shed is not less than 5 mm, and the thickness of the head portion which is to be covered with a cap or the thickness of the insulator in the vicinity of the junction portion between the head portion and the shed is not less than 2 times the minimum thickness of the shed.
摘要翻译： 抵抗弹丸破坏的瓷电绝缘体包括一个棚子和一个与梭口一体形成的头部。 梭口的最薄部分不小于5毫米，被帽盖的头部的厚度或在头部和梭口之间的接合部分附近的绝缘体的厚度不是 小于棚屋最小厚度的2倍。
-
48.发明申请公开(公告)号：US20110012201A1
公开(公告)日：2011-01-20
申请号：US12923308
申请日：2010-09-14
申请人： Atsushi Yagishita , Akio Kaneko
发明人： Atsushi Yagishita , Akio Kaneko
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/7854 , H01L29/78639
摘要： A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.
摘要翻译： 在衬底上形成线形绝缘体，然后用用作掩模的绝缘体蚀刻衬底，以在绝缘体的两侧形成第一沟槽。 侧壁绝缘体形成在第一沟槽的侧壁上，用绝缘体和侧壁绝缘体作为掩模蚀刻衬底，以在第一沟槽的底部形成第二沟槽。 之后，用作为抗氧化掩模的绝缘体和侧壁绝缘体氧化衬底，使得形成在位于衬底两侧的第二沟槽的相邻侧壁上形成的氧化物区域相互接触，并且绝缘体 和侧壁绝缘子被去除。 然后，在衬底中形成具有半导体区域作为线状翅片的翅片FET。
-
公开(公告)号：US07795682B2
公开(公告)日：2010-09-14
申请号：US11700147
申请日：2007-01-31
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。
-
公开(公告)号：US20100035396A1
公开(公告)日：2010-02-11
申请号：US12588336
申请日：2009-10-13
申请人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
发明人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/4908 , H01L29/785
摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.
摘要翻译： 本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。
-
-
-
-
-
-
-
-
-
搜索结果
58 条记录 (耗时 0.021 秒)
