公开(公告)号：US06363110B1

公开(公告)日：2002-03-26

申请号：US09729464

申请日：2000-12-04

申请人： Michael Oliver Polley ,  Alan Gatherer

发明人： Michael Oliver Polley ,  Alan Gatherer

IPC分类号： H04B138

CPC分类号： H04L27/2647 ,  H04L5/0007 ,  H04L5/0044 ,  H04L5/006 ,  H04L27/2608 ,  H04L27/2623

摘要： A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

公开(公告)号：US06201830B1

公开(公告)日：2001-03-13

申请号：US09096061

申请日：1998-06-11

申请人： Adam M. Chellali ,  Michael O. Polley ,  Alan Gatherer

发明人： Adam M. Chellali ,  Michael O. Polley ,  Alan Gatherer

IPC分类号： H04B138

CPC分类号： H04L1/0071 ,  H04L5/06

摘要： A method is described for reducing computational requirements during idle transmission in remote access systems incorporating digital subscriber line (DSL) modems, including asymmetrical DSL (ADSL) systems. Processing power is saved during idle transmission by generating an idle signal using low-complexity techniques. The generated idle signal is made spectrally compatible with xDSL systems, and a non-disruptive signaling scheme is used to indicate to the far-end receiver the transition between idle to active or active to idle status. A technique is presented that modulates the phase of the pilot tone to signal status transitions to the remote receiver. The computational complexity at the receiver is reduced because fill demodulation and decoding is not required to determine that an idle signal is being transmitted.

摘要翻译： 描述了一种用于在包括数字用户线（DSL）调制解调器的远程接入系统中的空闲传输期间减少计算需求的方法，包括不对称DSL（ADSL）系统。 通过使用低复杂度技术生成空闲信号，在空闲传输期间节省处理能力。 所产生的空闲信号与xDSL系统进行频谱兼容，并且使用非中断信令方案向远端接收机指示空闲到活动或主动到空闲状态之间的转换。 提出了一种技术，其调制导频音的相位以将状态转换为远程接收器。 由于不需要填充解调和解码来确定正在发送空闲信号，所以接收机的计算复杂度降低。

公开(公告)号：US6154497A

公开(公告)日：2000-11-28

申请号：US992553

申请日：1997-12-17

申请人： Alan Gatherer ,  John W. Fattaruso

发明人： Alan Gatherer ,  John W. Fattaruso

IPC分类号： H03M3/00 ,  H04B14/06

CPC分类号： H03M3/37 ,  H03M3/458

摘要： A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing recovery thereon to determine if any adjustment of the time adjustor (41, 141, 241) is required to minimize phase error and frequency error, and for producing the first adjustment signal (48, 148, 248) based on the results of the timing recovery. One time adjustor (41) includes a programmable delay line (46). Another time adjustor (141, 241) includes a two-part decimation filter (126, 226), a clock control (133, 233), and a clock divider (162, 262). An interpolation filter (270) may also be used as an aspect of the time adjustor (241). A method of converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) is also presented.

摘要翻译： 一种用于将模拟信号（18,118,218）转换为通信系统（10）中的数字信号（54,154,254）的转换（20,120,220），所述转换系统（20,120,220） ）包括用于接收过采样时钟信号（29,129,209）和所传输的模拟信号（18,118,218）的过采样模数转换器调制器（24,124,224），所述过采样模数转换器 数字转换器调制器（24,124,224），其可操作以对模拟信号（18,118,218）进行采样并将模拟信号（18,118,218）转换为第一数字信号（32,132,232）， 耦合到过采样模数转换器调制器（24,124,224）的时间调节器（41,141,241），用于接收第一数字信号（32,132,232）和第一调节信号（48,148 ，248）和用于产生输出数字信号（54,154,254）的数字信号处理器单元（56,156,256），以及耦合到时间调节器（41,141,241）的数字信号处理器单元（56,156,256），用于接收输出数字信号 （54，154，254 ）并执行其上的定时恢复以确定是否需要对时间调节器（41,141,241）进行任何调整以最小化相位误差和频率误差，并且基于结果产生第一调整信号（48,148,248） 的定时恢复。 一次调节器（41）包括可编程延迟线（46）。 另一时间调节器（141,241）包括两部分抽取滤波器（126,226），时钟控制（133,233）和时钟分频器（162,262）。 内插滤波器（270）也可以用作时间调节器（241）的一个方面。 还提出了一种将模拟信号（18,118,218）转换为数字信号（54,154,254）的方法。

公开(公告)号：US6055268A

公开(公告)日：2000-04-25

申请号：US667267

申请日：1996-06-20

申请人： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

发明人： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

IPC分类号： H04L29/10 ,  H04J11/00 ,  H04L1/00 ,  H04L1/16 ,  H04L5/14 ,  H04L25/03 ,  H04L25/49 ,  H04L27/26 ,  H04M11/00 ,  H04M11/06 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L1/0023 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0016 ,  H04L25/03 ,  H04L25/03343 ,  H04L25/4921 ,  H04L27/2647 ,  H04L27/2649 ,  H04L27/2675 ,  H04L5/1438 ,  H04M11/06 ,  H04M11/062 ,  H04L1/0059 ,  H04L1/16 ,  H04L2025/03414 ,  H04L2025/03611 ,  Y02B60/31 ,  Y02B60/36

摘要： A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).

摘要翻译： 具有接收和传输路径的调制解调器通信系统包括在传输路径中具有自适应滤波器（1532）的直接均衡器系统，以补偿通信信道的频率失真。 在由检测接收路径中的输入数据的数据检测器（1526）的控制下，发射机滤波器系数由滤波器系数计算器（1528）适配。 开关（1534）由发送输出数据缓冲器的状态控制，以将训练序列或输出数据复用到传输路径中。 当缓冲器空闲时，训练序列发生器（1540）链接到数模（D / A）转换器（1536）和线驱动器（1538）。 接收路径包括隔离开关（1520），接收放大器（1522）和限幅器（1524）。 接收器将接收到的训练序列与已知的训练序列进行相关，并使用诸如最小均方算法的自适应算法来更新均衡器滤波器系数。 第一实施例利用高速数字可编程滤波器（1532）。 另一个实施例利用周期性地填充由数字信号处理器（DSP）滤波的数据的数据缓冲器（1533）。

公开(公告)号：US07961758B2

公开(公告)日：2011-06-14

申请号：US12638578

申请日：2009-12-15

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： H04J3/24

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

公开(公告)号：US20110112606A1

公开(公告)日：2011-05-12

申请号：US12616932

申请日：2009-11-12

申请人： Alan Gatherer ,  Walter H. Schroen

发明人： Alan Gatherer ,  Walter H. Schroen

IPC分类号： A61N1/00

CPC分类号： A61N2/002 ,  A61N1/326 ,  A61N1/36103 ,  A61N1/36125 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) chip (100) expanded to nerve fiber (602) growth in the third dimension by through-silicon via-holes (TSV) (131), with an electrically conductive inner sidewall (303) having a roughness (303a) suitable for supporting the growing fiber and conductive connections (210) to the circuitry (101). The TSVs are fabricated parallel to each other and may be arrayed in regular patterns. The chip, provided with a pad (230) for contacting a nerve end and attaching a neuron, acts as a permanent protective sheath for the parallel growing fibers. Nerve fiber growth is stimulated by combining in the chip electrical and magnetic pulses and neurotrophic factors (603); continuous communication with external monitors is provided. The IC provides each TSV with a signal generator, electric and magnetic field generator, power source, potential sensor, and transceiver. The electronic signals may initiate a predetermined action potential in the adjacent nerve fiber end and a sensor is configured for sensing the action potential in the nerve fiber end.

摘要翻译： 通过硅通孔（TSV）（131）扩展到第三维度的神经纤维（602）生长的集成电路（IC）芯片，具有粗糙度的导电内侧壁（303） ）适合于将增长的光纤和导电连接（210）支撑到电路（101）。 TSV彼此平行地制造并且可以以规则图案排列。 设置有用于接触神经末端并附着神经元的垫（230）的芯片用作平行生长纤维的永久保护鞘。 神经纤维生长受到芯片电磁脉冲和神经营养因子的组合的刺激（603）; 提供与外部监视器的连续通信。 IC为每个TSV提供信号发生器，电场和磁场发生器，电源，电位传感器和收发器。 电子信号可以在相邻的神经纤维末端中发起预定的动作电位，并且传感器被配置用于感测神经纤维末端的动作电位。

公开(公告)号：US07634019B2

公开(公告)日：2009-12-15

申请号：US11466270

申请日：2006-08-22

申请人： Anand G. Dabak ,  Mohammed Nafie ,  Timothy M. Schmidl ,  Alan Gatherer

发明人： Anand G. Dabak ,  Mohammed Nafie ,  Timothy M. Schmidl ,  Alan Gatherer

IPC分类号： H04L1/02 ,  H04B1/38 ,  H04B1/00

CPC分类号： H01Q3/22 ,  H01Q1/2291 ,  H04B1/713 ,  H04B7/0615 ,  H04B7/0697 ,  H04B7/0848 ,  H04W84/18

摘要： A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second plurality of data signals. A transmit circuit (364) is coupled to receive the first plurality of data signals and transmit each data signal of the first plurality of data signals on a respective transmit frequency in a predetermined sequence of transmit frequencies. A receive circuit (362) is coupled to receive each data signal of the second plurality of data signals from a remote transmitter on the respective transmit frequency in the predetermined sequence. The receive circuit applies the second plurality of data signals to the signal processing circuit.

摘要翻译： 通信电路（28）被设计成具有被配置为产生第一多个数据信号并接收第二多个数据信号的信号处理电路（370）。 发射电路（364）被耦合以接收第一多个数据信号，并且以预定的发射频率的顺序在相应的发射频率上发射第一多个数据信号的每个数据信号。 接收电路（362）被耦合以便以预定顺序在相应发射频率上从远程发射机接收第二多个数据信号的每个数据信号。 接收电路将第二多个数据信号施加到信号处理电路。

公开(公告)号：US07386326B2

公开(公告)日：2008-06-10

申请号：US10235462

申请日：2002-09-04

申请人： Vijay Sundararajan ,  Sriram Sundararajan ,  Alan Gatherer

发明人： Vijay Sundararajan ,  Sriram Sundararajan ,  Alan Gatherer

IPC分类号： H04M1/00

CPC分类号： G06F9/24

摘要： A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.

摘要翻译： 提供了包括数据路径，微程序和微控制器的可编程协处理器系统。 数据路径包括可操作以接收输入信号的一个或多个数据路径元件。 微程序存储器包括可操作以控制数据路径以便处理输入信号的微程序。 微控制器可操作以基于修改命令修改微程序。

公开(公告)号：US07372825B1

公开(公告)日：2008-05-13

申请号：US09605610

申请日：2000-06-28

申请人： Timothy M. Schmidl ,  Alan Gatherer ,  Anand G. Dabak

发明人： Timothy M. Schmidl ,  Alan Gatherer ,  Anand G. Dabak

IPC分类号： H04Q7/00

CPC分类号： H04B7/2656

摘要： A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

摘要翻译： 一种无线通信系统（10）。 该系统包括发射机电路（BST 1），包括用于向第一小区（小区1）中的接收机发送多个帧的电路。 多个帧中的每一个包括位组（22），并且该位组将第一单元与第一单元相邻的第二单元（单元2）区分开。 发射机电路还包括用于将比特序列插入到比特组中的电路（54）。 该比特序列是从多个比特序列中选择的，使得发射机电路的连续传输包括多个 位序列。

公开(公告)号：US20060083174A1

公开(公告)日：2006-04-20

申请号：US11239498

申请日：2005-09-29

申请人： Byonghyo Shim ,  Yanni Chen ,  Manish Goel ,  Tod Wolf ,  Sriram Sundararajan ,  Alan Gatherer

发明人： Byonghyo Shim ,  Yanni Chen ,  Manish Goel ,  Tod Wolf ,  Sriram Sundararajan ,  Alan Gatherer

IPC分类号： H04L12/26

CPC分类号： G11C7/1075 ,  G06F13/1647 ,  G11C7/22

摘要： The present invention provides a collision avoidance manager for use with single-port memories. In one embodiment, the collision avoidance manager includes a memory structuring unit configured to provide a memory arrangement of the single-port memories having upper and lower memory banks arranged into half-memory portions. Additionally, the collision avoidance manager also includes a write memory alignment unit coupled to the memory structuring unit and configured to provide double-data writing to the memory arrangement based on memory collision avoidance. In a preferred embodiment, the collision avoidance manager also includes a read memory alignment unit coupled to the memory structuring unit and configured to provide double-data reading from the memory arrangement while maintaining the memory collision avoidance.

摘要翻译： 本发明提供了一种与单端口存储器一起使用的防碰撞管理器。 在一个实施例中，冲突避免管理器包括存储器结构单元，其被配置为提供具有布置成半存储器部分的上部和下部存储器组的单个端口存储器的存储器布置。 此外，防撞管理器还包括耦合到存储器构造单元并被配置为基于存储器冲突避免向存储器装置提供双数据写入的写存储器对准单元。 在优选实施例中，防碰撞管理器还包括耦合到存储器结构单元并被配置为在保持存储器冲突避免的同时从存储器装置提供双数据读取的读取存储器对准单元。