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公开(公告)号：US20100057823A1
公开(公告)日：2010-03-04
申请号：US12200037
申请日：2008-08-28
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.
摘要翻译： 公开了一种具有第一电路和第二电路的装置。 第一电路可以被配置为（i）通过在第一伽罗瓦域元件上执行第一伽罗瓦域反演来产生第二伽罗瓦域元件，第一伽罗瓦域反转与由高级加密标准定义的第二伽罗瓦域反演不同， ）通过将第二伽罗瓦域元素乘以预定矩阵的倒数来产生第三伽罗瓦域元素。 第二电路可以被配置为（i）通过在非跳过模式下处理当前加密循环中的第三伽罗瓦域元素来产生第四伽罗瓦域元素，（ii）通过将第四伽罗瓦域元素乘以第四伽罗瓦域元素 通过预定矩阵和（iii）在下一个加密轮次之前将第五伽罗瓦域元素呈现为第一伽罗瓦域元素的更新版本。
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公开(公告)号：US20090307543A1
公开(公告)日：2009-12-10
申请号：US12183512
申请日：2008-07-31
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译： 一种装置，包括控制器，多个传输电路和多个存储器控制电路。 控制器可以被配置为（i）呈现一个或多个命令，并且（ii）接收一个或多个响应。 多个传输电路中的每一个可以被配置为（i）接收命令之一，（ii）呈现响应，以及（iii）产生一个或多个控制信号。 多个存储器控制电路中的每一个可以（i）耦合到多个传输电路中的相应一个，并且（ii）被配置为（i）响应于一个或多个控制信号而产生一个或多个存储器访问信号 ，（ii）响应于所述一个或多个存储器访问信号，从相应存储器接收一个或多个存储器输出信号，以及（iii）响应于所述一个或多个存储器输出信号产生响应。 各个存储器可以独立地定尺寸。 控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。
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公开(公告)号：US20090300440A1
公开(公告)日：2009-12-03
申请号：US12167305
申请日：2008-07-03
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译： 一种包括第一电路和第二电路的存储器环。 第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。 在测试模式期间，可以将一个或多个数据序列呈现给存储器。 第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。
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44.发明申请CIPHER INDEPENDENT INTERFACE FOR CRYPTOGRAPHIC HARDWARE SERVICE 有权CIPHER独立接口用于CRYPTOGRAPHICAL HARDWARE SERVICE公开(公告)号：US20120121079A1
公开(公告)日：2012-05-17
申请号：US12673022
申请日：2009-04-10
IPC分类号： H04L9/28
CPC分类号： G06F21/602 , G09C1/00 , H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.
摘要翻译： 公开了一种密码独立的密码硬件服务。 密码独立事务被接收到输入时隙（202）中。 输入插槽包含用于保存事务的FIFO。 事务从密码独立形式转换为密码依赖格式（206），并且它们从FIFO中删除时的时序。 在通过密码特定硬件的密码处理之后，将结果发送到输出FIFO（212）。 可以使用多个FIFO和加密硬件，使得可以并行并且同时执行多个加密功能。
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公开(公告)号：US08160242B2
公开(公告)日：2012-04-17
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lay D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lay D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译： 一种包括初始化电路和散列计算电路的装置。 初始化电路可以被配置为呈现多个初始化值。 哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。 哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。
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公开(公告)号：US20110320397A1
公开(公告)日：2011-12-29
申请号：US12822349
申请日：2010-06-24
IPC分类号： G06N5/02
CPC分类号： G06N5/022 , G06F7/02 , G06F17/30985 , G06F2207/025 , G06N5/047
摘要： Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.
摘要翻译： 公开了一种用于匹配正则表达式的方法和装置。 维持每个符号的最后出现位置数的符号缓冲器。 当两个常数在正则表达式运算符的任一侧匹配时，查询符号缓冲区以确定正则表达式运算符的补码的成员是否在两个常量之间发生。 如果是这样，那么操作员不满意。 如果没有，那么操作员就满意了。
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公开(公告)号：US08046643B2
公开(公告)日：2011-10-25
申请号：US12183512
申请日：2008-07-31
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译： 一种装置，包括：控制器，被配置为呈现一个或多个命令并接收一个或多个响应;多个传输电路，被配置为接收命令中的一个，呈现响应，并产生一个或多个控制信号;以及多个存储器 - 控制电路，每个耦合到所述多个传输电路中的相应一个，并被配置为响应于所述一个或多个控制信号而产生一个或多个存储器访问信号，响应于所述控制电路响应于所述控制电路接收来自相应存储器的一个或多个存储器输出信号 一个或多个存储器访问信号，并且响应于一个或多个存储器输出信号而产生响应。 各个存储器可以独立地定尺寸。 控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。
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公开(公告)号：US20080270505A1
公开(公告)日：2008-10-30
申请号：US11741865
申请日：2007-04-30
IPC分类号： G06F7/00
CPC分类号： G06F7/724 , H04L9/0631 , H04L2209/122 , H04L2209/125
摘要： A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).
摘要翻译： 可以快速计算T
mm“file =”US20080270505A1-20081030-P00001.TIF“img-content =”character“img-format =”tif“/> n。 调度（调用乘法单元的频率）可以被认为是算法的参数。 所提出的“差分”单元的架构在速度（延迟）和面积（门数）方面都是有效的。
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