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公开(公告)号：US08160242B2
公开(公告)日：2012-04-17
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lay D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lay D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译： 一种包括初始化电路和散列计算电路的装置。 初始化电路可以被配置为呈现多个初始化值。 哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。 哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。
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公开(公告)号：US20100086127A1
公开(公告)日：2010-04-08
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译： 一种包括初始化电路和散列计算电路的装置。 初始化电路可以被配置为呈现多个初始化值。 哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。 哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。
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公开(公告)号：US20110029980A1
公开(公告)日：2011-02-03
申请号：US12902376
申请日：2010-10-12
IPC分类号： G06F9/46
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译： 公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。 第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。 第二电路可以被配置为响应于第一信号而产生多个第二信号。 第三电路可以被配置为响应于第二信号而产生多个使能信号。 第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。 第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。 可以独立于使能信号产生第二信号。
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公开(公告)号：US20100293421A1
公开(公告)日：2010-11-18
申请号：US12465810
申请日：2009-05-14
IPC分类号： G01R31/28
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译： 公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。 第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。 第二电路可以被配置为响应于第一信号而产生多个第二信号。 第三电路可以被配置为响应于第二信号而产生多个使能信号。 第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。 第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。 可以独立于使能信号产生第二信号。
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公开(公告)号：US20050005255A1
公开(公告)日：2005-01-06
申请号：US10602570
申请日：2003-06-24
申请人： Mikhail Grinchuk , Anatoli Bolotov
发明人： Mikhail Grinchuk , Anatoli Bolotov
CPC分类号： G06F17/5045 , G06F7/02 , G06F7/506
摘要： Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f′N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N′ inputs, where N′ is 3n or 2*3n, and the N′-N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N-1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.
摘要翻译： 用于逻辑运算的逻辑电路基于函数fN = x1 OR（x2 AND（x3 OR（x4 AND ... xN ...））或f'N = x1 AND（x2 OR（x3 AND（x4 OR。 通过基于2输入$和@门的预先选择的模式来定义逻辑电路的顶部来设计。 顶部有N个输入和大约N / 3个输出。 定义了较小的逻辑电路，其具有耦合到顶部部分的输出的大约N / 3个输入。 在一个实施例中，电路被设计用于具有N'个输入的电路，其中N'是3n或2 * 3n，并且N'-N个最高有效输入被设置为固定值。 额外的门被去除，导致最小的深度电路。 在另一个实施例中，通过设计用于N-1输入的电路并将电路变换成N输入电路，在一些情况下深度进一步降低。 根据功能，$和@门将转换为AND和/或OR门。
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公开(公告)号：US07949909B2
公开(公告)日：2011-05-24
申请号：US12183562
申请日：2008-07-31
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译： 存储器环包括第一电路，第二电路和第三电路。 第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。 第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。 第三电路可以被配置为生成一个或多个地址序列。 在测试模式期间将一个或多个地址序列呈现给存储器。
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公开(公告)号：US20190042795A1
公开(公告)日：2019-02-07
申请号：US16022402
申请日：2018-06-28
申请人： Anatoli Bolotov , Mikhail Grinchuk
发明人： Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G06F21/64 , G06F11/10 , G11C29/52 , G06F12/0815 , H04L9/08
摘要： System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter in the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.
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公开(公告)号：US08654969B2
公开(公告)日：2014-02-18
申请号：US12673022
申请日：2009-04-10
CPC分类号： G06F21/602 , G09C1/00 , H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.
摘要翻译： 公开了一种密码独立的密码硬件服务。 密码独立事务被接收到输入时隙（202）中。 输入插槽包含用于保存事务的FIFO。 这些事务从密码独立形式转换为密码依赖格式（206），并将它们从FIFO中删除。 在通过密码特定硬件的密码处理之后，将结果发送到输出FIFO（212）。 可以使用多个FIFO和加密硬件，使得可以并行并且同时执行多个加密功能。
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公开(公告)号：US08650146B2
公开(公告)日：2014-02-11
申请号：US12822349
申请日：2010-06-24
IPC分类号： G06N5/02
CPC分类号： G06N5/022 , G06F7/02 , G06F17/30985 , G06F2207/025 , G06N5/047
摘要： Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.
摘要翻译： 公开了一种用于匹配正则表达式的方法和装置。 维持每个符号的最后出现位置数的符号缓冲器。 当两个常数在正则表达式运算符的任一侧匹配时，查询符号缓冲区以确定正则表达式运算符的补码的成员是否在两个常量之间发生。 如果是这样，那么操作员不满意。 如果没有，那么操作员就满意了。
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公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译： 一种包括第一电路和第二电路的存储器环。 第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。 在测试模式期间，可以将一个或多个数据序列呈现给存储器。 第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。
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