公开(公告)号：US06560294B1

公开(公告)日：2003-05-06

申请号：US09393366

申请日：1999-09-10

申请人： Alan Gatherer

发明人： Alan Gatherer

IPC分类号： H04L512

CPC分类号： H04L27/3872

摘要： A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated signals, including phase and amplitude modulated signals such as quadrature amplitude modulation (QAM) information. The carrier recovery circuit (35) includes a phase detection function (40), preferably realized by way of programs executed by a digital signal processor, that generates a derivative signal (g(x″)) based upon a summation of a complex function of a corrected input signal (x″) over some or all of the possible points in the modulation constellation. In one embodiment of the invention, the derivative signal is an exact evaluation, considered over the sum of all points in the constellation; in another embodiment of the invention, only four small magnitude points, at relative quadrature phases, are included in the summation. Also disclosed is an embodiment of the invention in which a first order Taylor series operation is used upon QAM signals.

摘要翻译： 公开了一种包括具有改进的载波恢复电路（35）的解调器（25）的电缆调制解调器（20）。 电缆调制解调器（20）解调相位调制信号，包括诸如正交幅度调制（QAM）信息的相位和幅度调制信号。 载波恢复电路（35）包括相位检测功能（40），其优选地通过由数字信号处理器执行的程序来实现，其基于复函数的总和产生导数信号（g（x“）） 的校正输入信号（x“）在调制星座图中的一些或全部可能点上。 在本发明的一个实施例中，导数信号是对星座中所有点的总和进行考虑的精确估计; 在本发明的另一个实施例中，在相加正交相位中仅包括四个小幅值点。 还公开了本发明的实施例，其中在QAM信号上使用一阶泰勒级数操作。

公开(公告)号：US06549584B1

公开(公告)日：2003-04-15

申请号：US09345054

申请日：1999-06-30

申请人： Alan Gatherer ,  Murtaza Ali

发明人： Alan Gatherer ,  Murtaza Ali

IPC分类号： H04L512

CPC分类号： H03M13/256 ,  H03M13/23 ,  H03M13/25

摘要： A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes.

摘要翻译： 公开了一种包括最低有效位卷积编码方案的调制解调器（12）。 在调制解调器（12）的发送侧，包括编码器（28），其中使用卷积编码器（35I，35Q）来对编码器施加到相位和幅度调制星座的每个符号的每一位进行编码，优选最小 使得编码比特选择调制信号中的多个子星座中的一个。 每个编码器（35,35'）被布置为有限状态机，三十二或六十四个状态。 代码提供的最小汉明距离（dfree）为4，使得调制解调器的最终编码增益比传统的编码方式有所改善。

公开(公告)号：US06400769B1

公开(公告)日：2002-06-04

申请号：US09129070

申请日：1998-08-04

申请人： Alan Gatherer ,  Keith L. Quiring ,  Murtaza Ali

发明人： Alan Gatherer ,  Keith L. Quiring ,  Murtaza Ali

IPC分类号： H03B300

CPC分类号： H04Q3/0016 ,  H04Q2213/13003 ,  H04Q2213/13034 ,  H04Q2213/13102 ,  H04Q2213/13199 ,  H04Q2213/13298 ,  H04Q2213/13389

摘要： A linecard codec (250) eliminates limitations of companded code disclosed which increases data rates over a public switched telephone network. The network links a plurality of subscribers and services providers through a central office facility (25) which includes at least one digital backplane (150). The codec (250) comprises an analog interface (152) to the network and a converter (258) coupled to the analog interface and configured to convert analog signals from subscribers to linear coded data (259). A RAM table (262) is used to map the linear coded data (259) to a predetermined coding scheme based on the values stored in the RAM table (262). The RAM table (262) stores mapping values that determine a mapping function between data transmitted by a service provider on the digital backplane (150) and data transmitted to a subscriber.

摘要翻译： 线路编解码器（250）消除了公开的压缩码的限制，这增加了公共交换电话网络上的数据速率。 网络通过包括至少一个数字背板（150）的中心局设施（25）来连接多个订户和服务提供商。 编解码器（250）包括到网络的模拟接口（152）和耦合到模拟接口并被配置为将来自用户的模拟信号转换成线性编码数据（259）的转换器（258）。 RAM表（262）用于基于存储在RAM表（262）中的值将线性编码数据（259）映射到预定编码方案。 RAM表（262）存储确定由数字背板（150）上的服务提供商发送的数据与发送给用户的数据之间的映射函数的映射值。

公开(公告)号：US06363110B1

公开(公告)日：2002-03-26

申请号：US09729464

申请日：2000-12-04

申请人： Michael Oliver Polley ,  Alan Gatherer

发明人： Michael Oliver Polley ,  Alan Gatherer

IPC分类号： H04B138

CPC分类号： H04L27/2647 ,  H04L5/0007 ,  H04L5/0044 ,  H04L5/006 ,  H04L27/2608 ,  H04L27/2623

摘要： A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

公开(公告)号：US06201830B1

公开(公告)日：2001-03-13

申请号：US09096061

申请日：1998-06-11

申请人： Adam M. Chellali ,  Michael O. Polley ,  Alan Gatherer

发明人： Adam M. Chellali ,  Michael O. Polley ,  Alan Gatherer

IPC分类号： H04B138

CPC分类号： H04L1/0071 ,  H04L5/06

摘要： A method is described for reducing computational requirements during idle transmission in remote access systems incorporating digital subscriber line (DSL) modems, including asymmetrical DSL (ADSL) systems. Processing power is saved during idle transmission by generating an idle signal using low-complexity techniques. The generated idle signal is made spectrally compatible with xDSL systems, and a non-disruptive signaling scheme is used to indicate to the far-end receiver the transition between idle to active or active to idle status. A technique is presented that modulates the phase of the pilot tone to signal status transitions to the remote receiver. The computational complexity at the receiver is reduced because fill demodulation and decoding is not required to determine that an idle signal is being transmitted.

摘要翻译： 描述了一种用于在包括数字用户线（DSL）调制解调器的远程接入系统中的空闲传输期间减少计算需求的方法，包括不对称DSL（ADSL）系统。 通过使用低复杂度技术生成空闲信号，在空闲传输期间节省处理能力。 所产生的空闲信号与xDSL系统进行频谱兼容，并且使用非中断信令方案向远端接收机指示空闲到活动或主动到空闲状态之间的转换。 提出了一种技术，其调制导频音的相位以将状态转换为远程接收器。 由于不需要填充解调和解码来确定正在发送空闲信号，所以接收机的计算复杂度降低。

公开(公告)号：US6154497A

公开(公告)日：2000-11-28

申请号：US992553

申请日：1997-12-17

申请人： Alan Gatherer ,  John W. Fattaruso

发明人： Alan Gatherer ,  John W. Fattaruso

IPC分类号： H03M3/00 ,  H04B14/06

CPC分类号： H03M3/37 ,  H03M3/458

摘要： A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing recovery thereon to determine if any adjustment of the time adjustor (41, 141, 241) is required to minimize phase error and frequency error, and for producing the first adjustment signal (48, 148, 248) based on the results of the timing recovery. One time adjustor (41) includes a programmable delay line (46). Another time adjustor (141, 241) includes a two-part decimation filter (126, 226), a clock control (133, 233), and a clock divider (162, 262). An interpolation filter (270) may also be used as an aspect of the time adjustor (241). A method of converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) is also presented.

摘要翻译： 一种用于将模拟信号（18,118,218）转换为通信系统（10）中的数字信号（54,154,254）的转换（20,120,220），所述转换系统（20,120,220） ）包括用于接收过采样时钟信号（29,129,209）和所传输的模拟信号（18,118,218）的过采样模数转换器调制器（24,124,224），所述过采样模数转换器 数字转换器调制器（24,124,224），其可操作以对模拟信号（18,118,218）进行采样并将模拟信号（18,118,218）转换为第一数字信号（32,132,232）， 耦合到过采样模数转换器调制器（24,124,224）的时间调节器（41,141,241），用于接收第一数字信号（32,132,232）和第一调节信号（48,148 ，248）和用于产生输出数字信号（54,154,254）的数字信号处理器单元（56,156,256），以及耦合到时间调节器（41,141,241）的数字信号处理器单元（56,156,256），用于接收输出数字信号 （54，154，254 ）并执行其上的定时恢复以确定是否需要对时间调节器（41,141,241）进行任何调整以最小化相位误差和频率误差，并且基于结果产生第一调整信号（48,148,248） 的定时恢复。 一次调节器（41）包括可编程延迟线（46）。 另一时间调节器（141,241）包括两部分抽取滤波器（126,226），时钟控制（133,233）和时钟分频器（162,262）。 内插滤波器（270）也可以用作时间调节器（241）的一个方面。 还提出了一种将模拟信号（18,118,218）转换为数字信号（54,154,254）的方法。

公开(公告)号：US6055268A

公开(公告)日：2000-04-25

申请号：US667267

申请日：1996-06-20

申请人： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

发明人： William C. Timm ,  Walter Y. Chen ,  Gene A. Frantz ,  Domingo G. Garcia ,  Xiaolin Lu ,  Dennis G. Mannering ,  Michael O. Polley ,  Terence J. Riley ,  Donald P. Shaver ,  Song Wu ,  Alan Gatherer ,  Paul E. Schurr ,  Douglas B. Weiner

IPC分类号： H04L29/10 ,  H04J11/00 ,  H04L1/00 ,  H04L1/16 ,  H04L5/14 ,  H04L25/03 ,  H04L25/49 ,  H04L27/26 ,  H04M11/00 ,  H04M11/06 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L1/0023 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0016 ,  H04L25/03 ,  H04L25/03343 ,  H04L25/4921 ,  H04L27/2647 ,  H04L27/2649 ,  H04L27/2675 ,  H04L5/1438 ,  H04M11/06 ,  H04M11/062 ,  H04L1/0059 ,  H04L1/16 ,  H04L2025/03414 ,  H04L2025/03611 ,  Y02B60/31 ,  Y02B60/36

摘要： A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).

摘要翻译： 具有接收和传输路径的调制解调器通信系统包括在传输路径中具有自适应滤波器（1532）的直接均衡器系统，以补偿通信信道的频率失真。 在由检测接收路径中的输入数据的数据检测器（1526）的控制下，发射机滤波器系数由滤波器系数计算器（1528）适配。 开关（1534）由发送输出数据缓冲器的状态控制，以将训练序列或输出数据复用到传输路径中。 当缓冲器空闲时，训练序列发生器（1540）链接到数模（D / A）转换器（1536）和线驱动器（1538）。 接收路径包括隔离开关（1520），接收放大器（1522）和限幅器（1524）。 接收器将接收到的训练序列与已知的训练序列进行相关，并使用诸如最小均方算法的自适应算法来更新均衡器滤波器系数。 第一实施例利用高速数字可编程滤波器（1532）。 另一个实施例利用周期性地填充由数字信号处理器（DSP）滤波的数据的数据缓冲器（1533）。

公开(公告)号：US07961758B2

公开(公告)日：2011-06-14

申请号：US12638578

申请日：2009-12-15

申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

IPC分类号： H04J3/24

CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

公开(公告)号：US20110112606A1

公开(公告)日：2011-05-12

申请号：US12616932

申请日：2009-11-12

申请人： Alan Gatherer ,  Walter H. Schroen

发明人： Alan Gatherer ,  Walter H. Schroen

IPC分类号： A61N1/00

CPC分类号： A61N2/002 ,  A61N1/326 ,  A61N1/36103 ,  A61N1/36125 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) chip (100) expanded to nerve fiber (602) growth in the third dimension by through-silicon via-holes (TSV) (131), with an electrically conductive inner sidewall (303) having a roughness (303a) suitable for supporting the growing fiber and conductive connections (210) to the circuitry (101). The TSVs are fabricated parallel to each other and may be arrayed in regular patterns. The chip, provided with a pad (230) for contacting a nerve end and attaching a neuron, acts as a permanent protective sheath for the parallel growing fibers. Nerve fiber growth is stimulated by combining in the chip electrical and magnetic pulses and neurotrophic factors (603); continuous communication with external monitors is provided. The IC provides each TSV with a signal generator, electric and magnetic field generator, power source, potential sensor, and transceiver. The electronic signals may initiate a predetermined action potential in the adjacent nerve fiber end and a sensor is configured for sensing the action potential in the nerve fiber end.

摘要翻译： 通过硅通孔（TSV）（131）扩展到第三维度的神经纤维（602）生长的集成电路（IC）芯片，具有粗糙度的导电内侧壁（303） ）适合于将增长的光纤和导电连接（210）支撑到电路（101）。 TSV彼此平行地制造并且可以以规则图案排列。 设置有用于接触神经末端并附着神经元的垫（230）的芯片用作平行生长纤维的永久保护鞘。 神经纤维生长受到芯片电磁脉冲和神经营养因子的组合的刺激（603）; 提供与外部监视器的连续通信。 IC为每个TSV提供信号发生器，电场和磁场发生器，电源，电位传感器和收发器。 电子信号可以在相邻的神经纤维末端中发起预定的动作电位，并且传感器被配置用于感测神经纤维末端的动作电位。

公开(公告)号：US07386326B2

公开(公告)日：2008-06-10

申请号：US10235462

申请日：2002-09-04

申请人： Vijay Sundararajan ,  Sriram Sundararajan ,  Alan Gatherer

发明人： Vijay Sundararajan ,  Sriram Sundararajan ,  Alan Gatherer

IPC分类号： H04M1/00

CPC分类号： G06F9/24

摘要： A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.

摘要翻译： 提供了包括数据路径，微程序和微控制器的可编程协处理器系统。 数据路径包括可操作以接收输入信号的一个或多个数据路径元件。 微程序存储器包括可操作以控制数据路径以便处理输入信号的微程序。 微控制器可操作以基于修改命令修改微程序。