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70 条记录 (耗时 0.021 秒)

    Integrated BEOL thin film resistor
    42.
    发明授权
    Integrated BEOL thin film resistor 有权
    集成BEOL薄膜电阻

    公开(公告)号：US08093679B2

    公开(公告)日：2012-01-10

    申请号：US13023579

    申请日：2011-02-09

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/00 ,  H01L27/10 ,  H01L29/74 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

    Integrated BEOL thin film resistor
    44.
    发明授权
    Integrated BEOL thin film resistor 有权
    集成BEOL薄膜电阻

    公开(公告)号：US07902629B2

    公开(公告)日：2011-03-08

    申请号：US12271942

    申请日：2008-11-17

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/00 ,  H01L27/10 ,  H01L29/74 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

    Capacitor having electrode terminals at same end of capacitor to reduce parasitic inductance
    45.
    发明授权
    Capacitor having electrode terminals at same end of capacitor to reduce parasitic inductance 失效
    在电容器的同一端具有电极端子以减少寄生电感的电容器

    公开(公告)号：US07551421B2

    公开(公告)日：2009-06-23

    申请号：US11616064

    申请日：2006-12-26

    申请人： Eric Thompson ,  Anil K. Chinthakindi

    发明人： Eric Thompson ,  Anil K. Chinthakindi

    IPC分类号： H01G4/228 ,  H01G4/005

    CPC分类号： H01G4/306 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A capacitor is disclosed having reduced impedance. In one embodiment, the capacitor includes a cathode including a first terminal and a first set of electrodes extending from the first terminal in a first layer, each electrode in the first set coupled to one corresponding electrode of a second set of electrodes in a second layer by at least one contact; and an anode including a second terminal and a third set of electrodes extending from the second terminal in the second layer, each electrode in the third set coupled to one corresponding electrode of a fourth set of electrodes in the first layer by at least one contact, wherein the first terminal and the second terminal are on a same end of the capacitor.

    摘要翻译： 公开了具有减小的阻抗的​​电容器。 在一个实施例中，电容器包括阴极，其包括第一端子和从第一层中的第一端子延伸的第一组电极，第一组中的每个电极耦合到第二层中的第二组电极的一个对应电极 至少有一个联系人; 以及包括从第二层中的第二端子延伸的第二端子和第三组电极的阳极，第三组中的每个电极通过至少一个触点耦合到第一层中的第四组电极的一个对应电极， 其中所述第一端子和所述第二端子位于所述电容器的同一端上。

    High capacitance density vertical natural capacitors
    46.
    发明授权
    High capacitance density vertical natural capacitors 失效
    高电容密度垂直天然电容

    公开(公告)号：US07466534B2

    公开(公告)日：2008-12-16

    申请号：US11422457

    申请日：2006-06-06

    申请人： Anil K. Chinthakindi

    发明人： Anil K. Chinthakindi

    IPC分类号： H01G4/228 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

    摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

    摘要翻译： 公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。 该间隙宽度减小显着增加了电容器的电容密度。 通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。 一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。 可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的空气间隙，这将进一步增加电容密度并将封装电容器，以便使垂直板之间的距离减小。

    Capacitor having electrodes at different depths to reduce parasitic capacitance
    47.
    发明授权
    Capacitor having electrodes at different depths to reduce parasitic capacitance 失效
    电容器具有不同深度的电极以减少寄生电容

    公开(公告)号：US07456463B2

    公开(公告)日：2008-11-25

    申请号：US11671614

    申请日：2007-02-06

    申请人： Eric Thompson ,  Anil K. Chinthakindi

    发明人： Eric Thompson ,  Anil K. Chinthakindi

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01G4/33 ,  H01G4/228 ,  H01G4/306 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

    摘要翻译： 公开了具有降低的寄生电容的电容器。 在一个实施例中，电容器包括第一组电极，第一组的每个电极延伸穿过衬底上方的多个后端行（BEOL）层中的至少一个; 第二组电极，第二组的每个电极延伸穿过至少一个BEOL层，并且其中第二组的每个电极延伸到多个BEOL层的比第一组的每个电极更大的深度。

    CAPACITOR HAVING ELECTRODE TERMINALS AT SAME END OF CAPACITOR TO REDUCE PARASITIC INDUCTANCE
    49.
    发明申请
    CAPACITOR HAVING ELECTRODE TERMINALS AT SAME END OF CAPACITOR TO REDUCE PARASITIC INDUCTANCE 失效
    具有电极终端的电容器在电容器端部减少PARASITIC电感

    公开(公告)号：US20080151469A1

    公开(公告)日：2008-06-26

    申请号：US11616064

    申请日：2006-12-26

    申请人： Eric Thompson ,  Anil K. Chinthakindi

    发明人： Eric Thompson ,  Anil K. Chinthakindi

    IPC分类号： H01G4/005

    CPC分类号： H01G4/306 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A capacitor is disclosed having reduced impedance. In one embodiment, the capacitor includes a cathode including a first terminal and a first set of electrodes extending from the first terminal in a first layer, each electrode in the first set coupled to one corresponding electrode of a second set of electrodes in a second layer by at least one contact; and an anode including a second terminal and a third set of electrodes extending from the second terminal in the second layer, each electrode in the third set coupled to one corresponding electrode of a fourth set of electrodes in the first layer by at least one contact, wherein the first terminal and the second terminal are on a same end of the capacitor.

    摘要翻译： 公开了具有减小的阻抗的​​电容器。 在一个实施例中，电容器包括阴极，其包括第一端子和从第一层中的第一端子延伸的第一组电极，第一组中的每个电极耦合到第二层中的第二组电极的一个对应电极 至少有一个联系人; 以及包括从第二层中的第二端子延伸的第二端子和第三组电极的阳极，第三组中的每个电极通过至少一个触点耦合到第一层中的第四组电极的一个对应电极， 其中所述第一端子和所述第二端子位于所述电容器的同一端上。

    HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS
    50.
    发明申请
    HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS 失效
    高电容密度垂直自然电容器

    公开(公告)号：US20070279835A1

    公开(公告)日：2007-12-06

    申请号：US11422457

    申请日：2006-06-06

    申请人： Anil K. Chinthakindi

    发明人： Anil K. Chinthakindi

    IPC分类号： H01G4/228

    CPC分类号： H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

    摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

    摘要翻译： 公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。 该间隙宽度减小显着增加了电容器的电容密度。 通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。 一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。 可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的空气间隙，这将进一步增加电容密度并将封装电容器，以便使垂直板之间的距离减小。