公开(公告)号：US07643268B2

公开(公告)日：2010-01-05

申请号：US12194566

申请日：2008-08-20

申请人： Anil K. Chinthakindi

发明人： Anil K. Chinthakindi

IPC分类号： H01G4/228 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

摘要翻译： 公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。 该间隙宽度减小显着增加了电容器的电容密度。 通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。 一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。 可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的气隙，这将进一步增加电容密度并封装电容器，以使得垂直板之间的距离减小。

公开(公告)号：US07608909B2

公开(公告)日：2009-10-27

申请号：US11164765

申请日：2005-12-05

申请人： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

IPC分类号： H01L21/76

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20090032904A1

公开(公告)日：2009-02-05

申请号：US11831208

申请日：2007-07-31

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.

摘要翻译： 多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造，其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。 多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。 多个层包括相对于多个层中的其它层最靠近衬底的最底层。 最底层不包括连接到阳极端子的任何手指。

公开(公告)号：US20080305606A1

公开(公告)日：2008-12-11

申请号：US12194564

申请日：2008-08-20

申请人： Anil K. Chinthakindi

发明人： Anil K. Chinthakindi

IPC分类号： H01L21/20

CPC分类号： H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

公开(公告)号：US20080173981A1

公开(公告)日：2008-07-24

申请号：US11624712

申请日：2007-01-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

摘要翻译： 具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。 垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。 一对电容器板由板层和底板形成。 垂直对电容器板之间的电容电介质至少部分地是高k电介质。

公开(公告)号：US20080122574A1

公开(公告)日：2008-05-29

申请号：US11458494

申请日：2006-07-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC分类号： H01C1/06 ,  H01L21/20

CPC分类号： H01L27/0802 ,  H01L21/26513 ,  H01L28/20

摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

摘要翻译： 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

公开(公告)号：US07271700B2

公开(公告)日：2007-09-18

申请号：US10906365

申请日：2005-02-16

申请人： Anil K. Chinthakindi ,  Ebenezer E. Eshun

发明人： Anil K. Chinthakindi ,  Ebenezer E. Eshun

IPC分类号： H01C1/012

CPC分类号： H01L28/24 ,  H01C7/006 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor device and method of manufacture includes a layer of a thin film conductor material and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material and enables the said thin film resistor to carry higher current densities with reduced shift in resistance. In one embodiment, the thin film resistor device includes a single CDEL layer formed on one side (atop or underneath) the thin film conductor material. In a second embodiment, two CDEL layers are formed on both sides (atop and underneath) of the thin film conductor material. The resistor device may be manufactured as part of both BEOL and FEOL processes.

摘要翻译： 薄膜电阻器件及其制造方法包括薄膜导体材料层和电流密度增强层（CDEL）。 CDEL是适于粘附到薄膜导体材料的绝缘体材料，并且使得所述薄膜电阻器能够承受更高的电流密度，同时具有减小的电阻偏移。 在一个实施例中，薄膜电阻器件包括在薄膜导体材料的一侧（顶上或下面）形成的单个CDEL层。 在第二实施例中，在薄膜导体材料的两侧（顶上和下面）形成两个CDEL层。 电阻器件可以被制造为BEOL和FEOL工艺的一部分。

公开(公告)号：US20070158717A1

公开(公告)日：2007-07-12

申请号：US11306746

申请日：2006-01-10

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US06696343B1

公开(公告)日：2004-02-24

申请号：US10459978

申请日：2003-06-12

申请人： Anil K. Chinthakindi ,  Robert A. Groves ,  Kenneth J. Stein ,  Seshadri Subbanna ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Robert A. Groves ,  Kenneth J. Stein ,  Seshadri Subbanna ,  Richard P. Volant

IPC分类号： H01L2120

CPC分类号： H01G5/18 ,  B81B2201/01 ,  H01G5/011 ,  Y10S257/924

摘要： A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

摘要翻译： 描述了三维微机电（MEM）变容二极管，其中可移动光束和固定电极分别制造在彼此耦合的分开的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

公开(公告)号：US07910450B2

公开(公告)日：2011-03-22

申请号：US11276282

申请日：2006-02-22

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。