公开(公告)号：US08385135B2

公开(公告)日：2013-02-26

申请号：US12881940

申请日：2010-09-14

申请人： Antonino Conte ,  Alberto Jose Di Martino ,  Enrico Castaldo

发明人： Antonino Conte ,  Alberto Jose Di Martino ,  Enrico Castaldo

IPC分类号： G11C5/14 ,  G05F3/08

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0025

摘要： A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator.

摘要翻译： 一种用于产生操作电压并包括可变比较电压发生器，比较电压，包括多个有源器件的分隔支路的电压调节器，用于接收工作电压并提供相关的中间电压 和比较器，以接收比较电压和中间电压，并为调节电压发生器提供调节信号。

公开(公告)号：US20080273400A1

公开(公告)日：2008-11-06

申请号：US12113692

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G11C16/06

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.

摘要翻译： 一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。 该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将待写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入 在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。 该方法特别适用于闪速存储器。

公开(公告)号：US06906957B2

公开(公告)日：2005-06-14

申请号：US10662151

申请日：2003-09-12

申请人： Antonino Conte ,  Gianbattista Lo Giudice ,  Alfredo Signorello

发明人： Antonino Conte ,  Gianbattista Lo Giudice ,  Alfredo Signorello

IPC分类号： G11C16/28 ,  G11C7/00

CPC分类号： G11C16/28

摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路包括读出放大器，其具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的第一输入端的输出端 比较器，并具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端子的输出端子，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二 晶体管分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连互连点。

公开(公告)号：US20050030771A1

公开(公告)日：2005-02-10

申请号：US10877063

申请日：2004-06-24

申请人： Antonino Conte ,  Enrico Castaldo

发明人： Antonino Conte ,  Enrico Castaldo

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/073

摘要： A regulator circuit for a charge pump voltage generator comprises a voltage comparator means for performing a voltage comparison between a charge pump output voltage and a reference voltage, and means responsive to the voltage comparator means for conditioning a charge pump clocking to the result of the voltage comparison. The voltage comparator means includes sampling means for sampling the charge pump output voltage at a sampling rate. Sampling rate control means are provided, responsive to the voltage comparison, for controlling the sampling rate according to the result of the voltage comparison.

摘要翻译： 用于电荷泵电压发生器的调节器电路包括用于执行电荷泵输出电压和参考电压之间的电压比较的电压比较器装置，以及响应于电压比较器装置的装置，用于调节针对电压的结果的电荷泵时钟 比较。 电压比较器装置包括用于以采样率对电荷泵输出电压进行采样的采样装置。 提供响应于电压比较的采样率控制装置，用于根据电压比较的结果来控制采样率。

公开(公告)号：US06680643B2

公开(公告)日：2004-01-20

申请号：US10060870

申请日：2002-01-30

申请人： Antonino Conte ,  Oreste Concepito

发明人： Antonino Conte ,  Oreste Concepito

IPC分类号： G05F110

CPC分类号： G05F3/30

摘要： Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.

摘要翻译： 带隙型参考电压源，采用运算跨阻放大器。 带隙级由并联的第一和第二带隙分支形成; 第一带隙分支包括串联连接并形成第一输出节点的第一二极管和晶体管; 第二带隙分支包括串联连接并形成第二输出节点的第二二极管和第二晶体管。 运算放大器具有连接到带隙级的输出节点的输入。 放大器电流检测级连接到运算放大器的输出，并提供与运算放大器所绘制的电流相关的电流。 二极管电流检测级连接到放大器电流检测级的输出端和运算放大器的输出，并提供与流过第一二极管的电流相关的电流。 输出级将该电流转换成稳定的电压。

公开(公告)号：US20120002473A1

公开(公告)日：2012-01-05

申请号：US13170657

申请日：2011-06-28

申请人： Maria Giaquinta ,  Antonino Conte ,  Rosario Roberto Grasso ,  Francesco Nino Mammoliti

发明人： Maria Giaquinta ,  Antonino Conte ,  Rosario Roberto Grasso ,  Francesco Nino Mammoliti

IPC分类号： G11C16/10

CPC分类号： G11C5/14 ,  G11C5/141 ,  G11C16/30

摘要： An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition.

摘要翻译： 一种包括一组功能块的电子设备和用于产生用于功能块的一组偏置电压的偏置块。 该电子设备还包括一个保持块，该保持块耦合在偏置块和功能块之间，用于将每个偏置电压提供给至少一个对应的功能块，对于每个偏置电压，保持块包括用于存储偏置电压的电容元件，以及开关 元件可在其中提供从偏置块到电容元件的偏置电压到至少一个对应的功能块的累积条件之间切换，以及释放条件，其中将电容元件与偏置块隔离并提供来自电容 元件到所述至少一个对应的功能块，以及用于在所述累积条件和所述释放条件之间交替地切换所述开关元件的控制块。

公开(公告)号：US20110068179A1

公开(公告)日：2011-03-24

申请号：US12885028

申请日：2010-09-17

申请人： Gianbattista Lo Giudice ,  Enrico Castaldo ,  Antonino Conte

发明人： Gianbattista Lo Giudice ,  Enrico Castaldo ,  Antonino Conte

IPC分类号： G06K19/073 ,  G11C16/14 ,  G11C16/12

CPC分类号： G11C16/0433 ,  G11C16/10 ,  G11C16/16

摘要： Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.

摘要翻译： 这里描述了一种用于偏置由排列成行和列的存储器单元形成的EEPROM阵列的方法，每个可操作地耦合到第一开关和第二开关，并且具有通过第一开关选择性地连接到位线的第一导通端子， 选择性地可连接到通过第二开关的栅极控制线的控制终端，其中与每一行相关联的是分别连接到第一开关的控制端的第一字线和第二字线，以及分别操作地耦合到 同一行的存储单元。 该方法设想为给定的存储器操作选择至少一个存储器单元，偏置与其相关联的行的第一字线和第二字线，并且特别是以彼此不同的电压偏置第一和第二字线并且具有更高的值 而不是内部电源电压，并且是给定存储器操作的函数。

公开(公告)号：US07649786B2

公开(公告)日：2010-01-19

申请号：US11701165

申请日：2007-01-31

申请人： Antonino Conte ,  Roerto Annunziata ,  Paola Zuliani

发明人： Antonino Conte ,  Roerto Annunziata ,  Paola Zuliani

IPC分类号： G11C16/04

CPC分类号： G11C16/0433

摘要： A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.

摘要翻译： 存储器架构包括以行或字线和列或位线组织的EEPROM类型的至少一个存储器单元矩阵。 每个存储单元包括浮栅单元晶体管和选择晶体管，并连接到由矩阵共享的源极线。 存储器单元以字为单位，属于相同字的所有存储单元由字节开关驱动，该字节开关依次连接至至少一个控制栅极线。 存储单元还具有连接到第一附加线路的可访问基板端子。

公开(公告)号：US20080301356A1

公开(公告)日：2008-12-04

申请号：US12113709

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F13/00

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table.

摘要翻译： 一种方法是将数据写入非易失性存储器，其中包括在写入之前被擦除的存储器单元。 该方法包括以下步骤：提供包括目标页面的主非易失性存储器区域，提供包括辅助页面的辅助非易失性存储器区域，提供查找表以与无效目标页面的地址相关联的有效辅助地址 页面，并且响应于在目标页面中写入一条数据的命令以及在第一擦除的辅助页面中的目标页面的地址，使目标页面无效，并且更新查找页面， 桌子。

公开(公告)号：US07403441B2

公开(公告)日：2008-07-22

申请号：US11063649

申请日：2005-02-22

申请人： Enrico Castaldo ,  Antonino Conte ,  Salvatore Torrisi ,  Vincenzo Sambataro

发明人： Enrico Castaldo ,  Antonino Conte ,  Salvatore Torrisi ,  Vincenzo Sambataro

IPC分类号： G11C5/14

CPC分类号： G06F1/26 ,  G11C16/30

摘要： A power management unit for a non-volatile memory device is proposed. The power management unit includes means for providing a reference voltage, resistive means for deriving a reference current from the reference voltage, means for generating a plurality of operative voltages from a power supply voltage, and means for regulating the operative voltages; in the power management unit of the invention, for each operative voltage the means for regulating includes means for deriving a scaled reference current from the reference current according to a scaling factor, further resistive means for deriving a rating voltage from the scaled reference current, means for deriving a measuring voltage from the operative voltage and the rating voltage, and means for controlling the operative voltage according to a comparison between the measuring voltage and the reference voltage.

摘要翻译： 提出了一种用于非易失性存储器件的电源管理单元。 电源管理单元包括用于提供参考电压的装置，用于从参考电压导出参考电流的电阻装置，用于从电源电压产生多个工作电压的装置，以及用于调节工作电压的装置; 在本发明的电源管理单元中，对于每个操作电压，用于调节的装置包括用于根据缩放因子从参考电流导出缩放的参考电流的装置，用于从缩放的参考电流导出额定电压的另外的电阻装置， 用于从操作电压和额定电压导出测量电压，以及用于根据测量电压和参考电压之间的比较来控制工作电压的装置。