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    Apparatus and method for efficient division performance
    41.
    发明授权
    Apparatus and method for efficient division performance 有权
    用于有效划分性能的装置和方法

    公开(公告)号：US09524143B2

    公开(公告)日：2016-12-20

    申请号：US14315940

    申请日：2014-06-26

    Applicant: ARM Limited

    Inventor： Neil Burgess ,  David Raymond Lutz

    IPC: G06F7/535 ,  G06F9/30 ,  G06F7/537 ,  G06F5/01

    CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F7/537 ,  G06F9/3001

    Abstract: A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2N, where N is a positive integer, and bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits.

    Abstract translation: 提供了一种操作这种数据处理装置的数据处理装置和方法，用于响应分割指令执行除法运算，以通过将由除法指令指定的输入分子除以由分割器指定的输入分母来产生结果值 指令。 输入分子和输入分母是二进制值。 该装置包括分配电路，其被配置为通过执行除法运算来产生结果值，二次检测电路被配置为在输入分母具有由±2N给出的值时发出旁路条件，其中N是正整数， 以及旁路电路，响应于旁路条件的信号，配置为使旁路分路电路，并且使输出分子移位N位时产生结果值。

    Data processing apparatus and method for multiplying floating point operands
    42.
    发明授权
    Data processing apparatus and method for multiplying floating point operands 有权
    用于乘法运算的数据处理装置和方法

    公开(公告)号：US09483232B2

    公开(公告)日：2016-11-01

    申请号：US14200923

    申请日：2014-03-07

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G06F7/487 ,  G06F5/01 ,  G06F7/499 ,  G06F7/533

    CPC classification number: G06F7/4876 ,  G06F5/012 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/5336 ,  G06F2207/483

    Abstract: A data processing apparatus and method are provided for multiplying first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalized version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalized floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalized result significand. Thereafter, the normalized result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, while correctly rounding the result in situations where the result is subnormal.

    Abstract translation: 提供了一种数据处理装置和方法，用于对第一和第二标准化浮点操作数进行乘法，以便产生结果，每个归一化浮点操作数包括有效位数和指数。 指数确定电路用于计算结果的归一化版本的结果指数，并且舍入值生成电路然后通过将第一方向上的舍入常数移位取决于结果指数的移位量来生成舍入值。 部分产品生成电路将第一和第二标准化浮点运算数的有效数乘以生成第一和第二部分乘积，然后将第一和第二部分乘积与舍入值一起加在一起，以便生成归一化结果 有意义 此后，归一化结果有效位置在与第一方向相反的第二方向上移位移位量，以产生舍入结果有效。 这提供了一种用于乘以浮点数的特别有效的机制，同时在结果为非正常的情况下正确地舍入结果。

    Data processing apparatus having SIMD processing circuitry
    43.
    发明授权
    Data processing apparatus having SIMD processing circuitry 有权
    具有SIMD处理电路的数据处理装置

    公开(公告)号：US09292298B2

    公开(公告)日：2016-03-22

    申请号：US13936576

    申请日：2013-07-08

    Applicant: ARM LIMITED

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G06F7/38 ,  G06F15/00 ,  G06F9/38

    CPC classification number: G06F9/3887 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036

    Abstract: A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.

    Abstract translation: 数据处理装置具有排列电路，用于执行用于改变至少一个源操作数的数据元素大小或数据元素定位以产生第一和第二SIMD操作数的置换操作，以及用于在第一和第二操作数上执行SIMD操作的SIMD处理电路 SIMD操作数。 响应于需要置换操作的第一SIMD指令，指令解码器控制置换电路以执行置换操作以产生第一和第二SIMD操作数，然后控制SIMD处理电路以使用这些操作数执行SIMD操作。 响应于不需要置换操作的第二SIMD指令，指令解码器控制SIMD处理电路，使用由指令识别的第一和第二SIMD操作数来执行SIMD操作，而不通过置换电路。

    Apparatus and method for performing an index operation
    45.
    发明授权
    Apparatus and method for performing an index operation 有权

    公开(公告)号：US11113028B2

    公开(公告)日：2021-09-07

    申请号：US16521740

    申请日：2019-07-25

    Applicant: Arm Limited

    Inventor： Xiaoyang Shen ,  David Raymond Lutz ,  Cédric Denis Robert Airaud

    IPC: G06F7/527 ,  G06F16/22

    Abstract: An apparatus and method are provided for performing an index operation. The apparatus has vector processing circuitry to perform an index operation in each of a plurality of lanes of parallel processing. The index operation requires an index value opm to be multiplied by a multiplier value e to produce a multiplication result. The number of lanes of parallel processing is dependent on a specified element size, and the multiplier value is different, but known, for each lane of parallel processing. The vector processing circuitry comprises mapping circuitry to perform, within each lane, mapping operations on the index value opm in order to generate a plurality of intermediate input values. The plurality of intermediate input values are such that the addition of the plurality of intermediate input values produces the multiplication result. Within each lane the mapping operations are determined by the multiplier value used for that lane. The vector processing circuitry also has vector adder circuitry to perform, within each lane, an addition of at least the plurality of intermediate input values, in order to produce a result vector providing a result value for the index operation performed in each lane. This provides a high performance, low latency, technique for vectorising index operations.

    Anchored data element conversion
    46.
    发明授权
    Anchored data element conversion 有权

    公开(公告)号：US10963245B2

    公开(公告)日：2021-03-30

    申请号：US16424718

    申请日：2019-05-29

    Applicant: Arm Limited

    Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds ,  Nigel John Stephens

    IPC: G06F9/30 ,  H03M7/24

    Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

    Arithmetic operation input-output equality detection
    47.
    发明授权
    Arithmetic operation input-output equality detection 有权

    公开(公告)号：US09990179B2

    公开(公告)日：2018-06-05

    申请号：US15169996

    申请日：2016-06-01

    Applicant: ARM LIMITED

    Inventor： Christopher Neal Hinds ,  David Raymond Lutz

    IPC: G06F7/48 ,  G06F7/485

    CPC classification number: G06F7/485 ,  G06F7/48

    Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

    Apparatus and method for floating-point multiplication
    48.
    发明授权
    Apparatus and method for floating-point multiplication 有权

    公开(公告)号：US09823897B2

    公开(公告)日：2017-11-21

    申请号：US14865342

    申请日：2015-09-25

    Applicant: ARM LIMITED

    Inventor： David Raymond Lutz

    IPC: G06F7/44 ,  G06F7/487 ,  G06F5/01

    CPC classification number: G06F7/487 ,  G06F5/012

    Abstract: An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands. An unbiased result exponent is determined from operand exponent values and leading zero counts, and a shift amount and direction for a product significand as needed for a predetermined minimum exponent value of a predetermined canonical format. First and second rounding values for injection into addition of the partial products are generated by shifting a predetermined rounding pattern by the shift amount in an opposite shift direction for the first rounding value and left shifting by one bit the first rounding value to give the second. The first and second partial products are added together with the first rounding value to give a first product significand, and are added together with the second rounding value to give a second product significand. These product significands are shifted by the shift amount in the shift direction and one is then selected in order to generate a formatted significand in the predetermined canonical format. The early injection rounding provides a faster floating-point multiplier.

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