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    Memory for Artificial Neural Network Accelerator
    42.
    发明申请
    Memory for Artificial Neural Network Accelerator 有权

    公开(公告)号：US20220351032A1

    公开(公告)日：2022-11-03

    申请号：US17242721

    申请日：2021-04-28

    Applicant: Arm Limited

    Inventor： Teyuh Alice Chou ,  Mudit Bhargava ,  Supreet Jeloka ,  Fernando Garcia Redondo ,  Paul Nicholas Whatmough

    IPC: G06N3/063 ,  G06F17/16

    Abstract: A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.

    Devices and methods for controlling write operations
    43.
    发明授权
    Devices and methods for controlling write operations 有权

    公开(公告)号：US11423985B2

    公开(公告)日：2022-08-23

    申请号：US16582743

    申请日：2019-09-25

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

    IPC: G11C13/00

    Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

    MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS
    44.
    发明申请
    MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS 有权

    公开(公告)号：US20220208265A1

    公开(公告)日：2022-06-30

    申请号：US17139059

    申请日：2020-12-31

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Mudit Bhargava ,  Pranay Prabhat ,  Supreet Jeloka

    IPC: G11C13/00 ,  G11C11/16

    Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

    Memory for an Artificial Neural Network Accelerator
    46.
    发明申请
    Memory for an Artificial Neural Network Accelerator 有权

    公开(公告)号：US20220164137A1

    公开(公告)日：2022-05-26

    申请号：US17103629

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

    IPC: G06F3/06 ,  G06N3/063

    Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.

    TSV Coupled Integrated Circuits and Methods
    47.
    发明申请
    TSV Coupled Integrated Circuits and Methods 有权

    公开(公告)号：US20220130816A1

    公开(公告)日：2022-04-28

    申请号：US17077532

    申请日：2020-10-22

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

    IPC: H01L27/02 ,  H01L25/065 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00 ,  G06F30/31

    Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

    Multi-die integrated circuits with improved testability
    50.
    发明授权
    Multi-die integrated circuits with improved testability 有权

    公开(公告)号：US10825745B1

    公开(公告)日：2020-11-03

    申请号：US16666816

    申请日：2019-10-29

    Applicant: Arm Limited

    Inventor： Saurabh Pijuskumar Sinha ,  Xiaoqing Xu ,  Joel Thornton Irby ,  Mudit Bhargava

    IPC: H01L21/66 ,  H01L25/18 ,  G06F30/30 ,  G06F30/333

    Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

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