公开(公告)号：US06806147B1

公开(公告)日：2004-10-19

申请号：US10211190

申请日：2002-08-01

Applicant: Bin Yu ,  Che-Hoo Ng

Inventor： Bin Yu ,  Che-Hoo Ng

IPC: H01L21336

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092

Abstract: The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Abstract translation: 本发明提供了用于电分离n沟道和p沟道MOSFET的改进的阱结构。 本发明首先在基底中形成浅井。 然后在浅井下面形成掩埋非晶层。 然后在埋入的非晶层下方形成深井。 然后对衬底进行快速热退火以使埋入的非晶层重结晶。 井结构由浅井和深井组成。 然后可以在阱结构之上形成常规的半导体器件。 掩埋非晶层在形成深井期间抑制沟道效应，而不需要倾斜角。

公开(公告)号：US06787406B1

公开(公告)日：2004-09-07

申请号：US10638334

申请日：2003-08-12

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66803 ,  Y10S438/944

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract translation: 一种方法有助于掺杂包括衬底的半导体器件的散热片。 该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。 该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

公开(公告)号：US06785240B1

公开(公告)日：2004-08-31

申请号：US09585738

申请日：2000-06-02

Applicant: Jin Cao ,  R. Drew Davis ,  Scott Alan Vander Wiel ,  Bin Yu

Inventor： Jin Cao ,  R. Drew Davis ,  Scott Alan Vander Wiel ,  Bin Yu

IPC: H04J116

CPC classification number: H04L43/067 ,  H04L41/0213 ,  H04L41/142 ,  H04L41/16 ,  H04L43/045 ,  H04L43/0888

Abstract: In many packetized communication networks, it is not feasible to obtain exact counts of traffic (OD counts) between specific origin-destination node pairs, because the link counts that are readily obtainable at router interfaces are aggregated indiscriminately over OD pairs. The best that can be done is to make a probabilistic inference concerning the OD counts from the observed link counts. Such an inference relies upon a known linear relationship between observed link counts and unknown OD counts, and a statistical model describing how the values of the OD and link counts are probabilistically distributed. Disclosed is an improved method for making such inferences. The disclosed method takes explicit account of past data when forming a current estimate of the OD counts. As a consequence, behavior that evolves in time is described with improved accuracy and smoothness.

Abstract translation: 在许多打包通信网络中，在特定的起始 - 目的地节点对之间获得精确的业务计数（OD计数）是不可行的，因为在路由器接口上容易获得的链路计数在OD对上不加区分地聚合。 可以做的最好的事情是从观察到的链接数量中对OD计数进行概率推断。 这样的推论依赖于观察到的链接计数和未知OD计数之间已知的线性关系，以及描述OD和链接计数值如何概率分布的统计模型。 公开了一种用于进行这种推断的改进方法。 当形成OD计数的当前估计时，所公开的方法明确地考虑过去数据。 因此，在时间上演变的行为以提高的准确性和平滑性来描述。

公开(公告)号：US06764908B1

公开(公告)日：2004-07-20

申请号：US10173770

申请日：2002-06-19

Applicant: Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1054 ,  H01L21/823807

Abstract: A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。 实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动 当前。

公开(公告)号：US06762483B1

公开(公告)日：2004-07-13

申请号：US10348910

申请日：2003-01-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L2906

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06756643B1

公开(公告)日：2004-06-29

申请号：US10459579

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US06746926B1

公开(公告)日：2004-06-08

申请号：US09844752

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.

Abstract translation: 一种改进深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法。 该方法包括形成在沟道区域中而不是在源极/漏极结中的高度局部化的卤素注入。 通过移除临时间隔物形成的间隙进行晕轮植入。 然后，MOSFET进一步完成。

公开(公告)号：US06680250B1

公开(公告)日：2004-01-20

申请号：US10145740

申请日：2002-05-16

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。 然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。 非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开 非晶化过程。 激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。 因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。 因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。 因此，由于距离范围缺陷导致的结漏电减少。

公开(公告)号：US06664146B1

公开(公告)日：2003-12-16

申请号：US09873170

申请日：2001-06-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: For fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, a first hardmask is formed on a first area of the semiconductor substrate, and a first dielectric forming dopant is implanted into a second area of the semiconductor substrate that is not covered by the first hardmask. The first hardmask is removed from the first area of the semiconductor substrate. A second hardmask is formed on the second area of the semiconductor substrate, and a second dielectric forming dopant is implanted into the first area of the semiconductor substrate that is not covered by the second hardmask. A thermal anneal is performed to form a first buried insulating structure from the second dielectric forming dopant reacting within the first area of the semiconductor substrate and to form a second buried insulating structure from the first dielectric forming dopant reacting within the second area of the semiconductor substrate. A first semiconductor structure remains on top of the first buried insulating structure and has a different thickness from a second semiconductor structure remaining on top of the second buried insulating structure.

Abstract translation: 为了在SOI（绝缘体上半导体）技术中制造具有半导体衬底的场效应晶体管，在半导体衬底的第一区域上形成第一硬掩模，并且将第一电介质形成掺杂剂注入到半导体衬底的第二区域 没有被第一个硬掩模覆盖。 第一硬掩模从半导体衬底的第一区域去除。 第二硬掩模形成在半导体衬底的第二区域上，并且第二电介质形成掺杂剂注入到半导体衬底的未被第二硬掩模覆盖的第一区域中。 进行热退火，以形成第一掩埋绝缘结构，从第二电介质形成掺杂剂在半导体衬底的第一区域内反应，并形成第二掩埋绝缘结构，从第一电介质形成掺杂剂在半导体衬底的第二区域内反应 。 第一半导体结构保留在第一掩埋绝缘结构的顶部，并且具有与保留在第二掩埋绝缘结构的顶部上的第二半导体结构不同的厚度。

公开(公告)号：US06657276B1

公开(公告)日：2003-12-02

申请号：US10163925

申请日：2002-06-06

Applicant: Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

Inventor： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC: H01L2900

CPC classification number: H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract translation: 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。