公开(公告)号：US11238796B2

公开(公告)日：2022-02-01

申请号：US16334539

申请日：2018-06-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/3258

Abstract: This disclosure discloses a pixel circuit and a control method therefor, a display substrate and a display device. The pixel circuit comprises a first transistor, a second transistor, a third transistor, a storage capacitor and a light-emitting element. The pixel circuit further comprises a first sensing circuit and a second sensing circuit, wherein the first sensing circuit is connected in parallel with the first transistor, and the second sensing circuit is connected in parallel with the second transistor; a first sensing signal and a second sensing signal are respectively input to the first sensing circuit and the second sensing circuit for completing acquisition of electrical parameters of the pixel circuit according to the first sensing signal and the second sensing signal.

公开(公告)号：US11211027B2

公开(公告)日：2021-12-28

申请号：US16084027

申请日：2018-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Liugang Zhou ,  Haoliang Zheng ,  Yaoqiu Jing ,  Mingfu Han ,  Seungwoo Han

IPC: G09G3/36

Abstract: The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.

公开(公告)号：US11094277B2

公开(公告)日：2021-08-17

申请号：US16149432

申请日：2018-10-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang ,  Xing Yao ,  Lijun Yuan ,  Zhichong Wang ,  Mingfu Han ,  Yinglong Huang

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.

公开(公告)号：US10943552B2

公开(公告)日：2021-03-09

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik Im ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US10453413B2

公开(公告)日：2019-10-22

申请号：US15565756

申请日：2017-03-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36 ,  G09G3/20 ,  G09G3/3225 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines.

公开(公告)号：US10330975B2

公开(公告)日：2019-06-25

申请号：US15794298

申请日：2017-10-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhihe Jin ,  Seungwoo Han ,  Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Zhichong Wang ,  Lijun Yuan ,  Haoliang Zheng ,  Yunsik Im

IPC: G02F1/133 ,  G02F1/13357 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/19

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.

公开(公告)号：US10283039B2

公开(公告)日：2019-05-07

申请号：US15529731

申请日：2016-11-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hyunsic Choi ,  Seungwoo Han

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level.

公开(公告)号：US10217427B2

公开(公告)日：2019-02-26

申请号：US15513952

申请日：2016-02-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuanbo Zhang ,  Seungwoo Han ,  Xing Yao

IPC: G09G3/36

Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.

公开(公告)号：US20180336842A1

公开(公告)日：2018-11-22

申请号：US15533761

申请日：2016-12-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/34 ,  H04N5/369

CPC classification number: G09G3/34 ,  G09G3/3685 ,  G09G2320/0252 ,  H04N5/3698

Abstract: The present application discloses a method for driving a display panel, including receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel; determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data; determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein an amplitude of the overdrive voltage is greater than an amplitude of the initial driving voltage; and applying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to a same one subpixel for displaying a subpixel image associated with each frame of image data.

公开(公告)号：US09905155B2

公开(公告)日：2018-02-27

申请号：US14906781

申请日：2015-07-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuanbo Zhang ,  Seungwoo Han ,  Haoliang Zheng

IPC: G09G3/36 ,  G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28 ,  G11C19/287

Abstract: The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit.