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公开(公告)号：US07457393B2
公开(公告)日：2008-11-25
申请号：US11025771
申请日：2004-12-29
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/18 , H04L7/0008 , H04L7/0025 , H04L7/10
摘要： A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.
摘要翻译： 全局时钟恢复电路和端口电路确定并组合多个数据信号的静态相位调整信息和动态相位调整信息。 为多个数据信号中的每一个确定静态相位调整信息，并且为多个数据信号共同确定动态相位调整信息。
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公开(公告)号：US07403053B2
公开(公告)日：2008-07-22
申请号：US10325605
申请日：2002-12-19
申请人： Bryan K. Casper , Stephen R. Mooney
发明人： Bryan K. Casper , Stephen R. Mooney
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/135 , H04L7/0008 , H04L7/0025
摘要： An integrated circuit compensates for power supply voltage dependent delay using a clock circuit that is responsive to a power supply voltage measuring circuit. The clock circuit modifies a phase relationship based on a measured power supply voltage value.
摘要翻译： 集成电路使用响应于电源电压测量电路的时钟电路补偿电源电压相关的延迟。 时钟电路基于测量的电源电压值修改相位关系。
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公开(公告)号：US06621330B1
公开(公告)日：2003-09-16
申请号：US10162936
申请日：2002-06-04
IPC分类号： H03B100
CPC分类号： H03H15/00
摘要： A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter and a current multiplier in a single stage so as to provide a current signal indicative of a weighted sampled voltage signal. The current signals are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential.
摘要翻译： 离散时间模拟滤波器，其中滤波器的滤波器抽头包括电压 - 电流转换器和单级中的电流倍增器，以便提供指示加权采样电压信号的电流信号。 当前信号由一个或多个有源共源共栅差分锁存器相加以提供指示滤波输出的输出逻辑信号。 离散时间模拟滤波器可用于信道均衡，适用于高数据速率和低电压应用。 电压和电流信号可能是差分的。
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公开(公告)号：US07031221B2
公开(公告)日：2006-04-18
申请号：US10749677
申请日：2003-12-30
CPC分类号： G11C7/1066 , G11C7/10 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/1093
摘要： In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，芯片包括分别提供第一和第二接收数据信号的第一和第二端口以及第一和第二接收选通信号。 内部时钟信号与第一接收选通信号具有固定的相位关系，第二接收选通信号与内部时钟信号具有任意的相位关系。 第一和第二写入块分别与第一和第二接收选通信号同步地锁存第一和第二接收数据信号。 描述和要求保护其他实施例。
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公开(公告)号：US06933781B2
公开(公告)日：2005-08-23
申请号：US10426766
申请日：2003-04-30
IPC分类号： H03F1/48 , H03F3/45 , H03K19/0175 , H03K19/0185
CPC分类号： H03F1/486 , H03F3/4521 , H03F2200/36 , H03K19/01759 , H03K19/018592
摘要： An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.
摘要翻译： 放大器包括多个阶段。 多级放大器的早期阶段具有较低的增益并保持带宽。
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公开(公告)号：US06791399B2
公开(公告)日：2004-09-14
申请号：US10268865
申请日：2002-10-09
申请人： James E. Jaussi , Stephen R. Mooney
发明人： James E. Jaussi , Stephen R. Mooney
IPC分类号： H03B100
CPC分类号： H03H15/00
摘要： A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.
摘要翻译： 离散时间模拟滤波器，其中滤波器的滤波器抽头包括电压 - 电流转换器，有源电流镜和电流倍增器，以提供指示加权采样电压信号的电流信号。 来自滤波器抽头的当前信号由一个或多个有源共源共栅差分锁存器相加以提供指示滤波输出的输出逻辑信号。 离散时间模拟滤波器可用于信道均衡，适用于高数据速率和低电压应用。 电压和电流信号可能是差分的。 电压 - 电流转换器可以包括用于抑制共模电压变化的共模高通滤波器。
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公开(公告)号：US06453422B1
公开(公告)日：2002-09-17
申请号：US09470686
申请日：1999-12-23
IPC分类号： G06F126
CPC分类号： H04L12/40032 , H04L12/4013
摘要： According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.
摘要翻译： 根据本发明的实施例，要耦合到参考电压线的电路。 电路包括噪声耦合电路，其基于驱动器是否驱动数据线，将来自电路的噪声耦合到参考电压线。
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48.发明授权Using a timing strobe for synchronization and validation in a digital logic device 有权在数字逻辑器件中使用定时选通器进行同步和验证公开(公告)号：US06437601B1
公开(公告)日：2002-08-20
申请号：US09752906
申请日：2000-12-26
申请人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人： Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号： H03K19096
CPC分类号： G11C7/222 , G11C7/22 , H03L7/00 , H03L7/0812 , H04L7/0008
摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.
摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。
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公开(公告)号：US06424175B1
公开(公告)日：2002-07-23
申请号：US09659499
申请日：2000-09-11
IPC分类号： H03K1716
CPC分类号： H03K19/00384
摘要： A biased control loop for setting the impedance of an output driver includes a dummy driver having a variable output impedance, a sample and compare circuit to compare the output impedance of dummy output driver to a reference, and an up/down counter to modify the impedance. When the loop is locked, an error signal alternates positive and negative about a reference value. A digital filter produces a filtered version of the error signal with an apparent error value that does not alternate. The digital filter has a biased lock circuit that guarantees that the apparent error does not alternate. A simultaneous bidirectional port includes an output driver and the biased control loop to set the output driver impedance. When the output driver drives a bidirectional line and serves as a termination impedance for another driver, the reduced apparent error variation provides improved impedance matching.
摘要翻译： 用于设置输出驱动器的阻抗的偏置控制环路包括具有可变输出阻抗的虚拟驱动器，用于将虚拟输出驱动器的输出阻抗与参考值进行比较的采样和比较电路以及用于修改阻抗的上/下计数器 。 当环路被锁定时，错误信号会围绕参考值交替正负。 数字滤波器产生误差信号的滤波版本，具有不交替的明显误差值。 数字滤波器具有偏置的锁定电路，保证视在误差不会交替。 同时双向端口包括输出驱动器和偏置控制环路以设置输出驱动器阻抗。 当输出驱动器驱动双向线并用作另一个驱动器的终端阻抗时，减小的视差误差提供改进的阻抗匹配。
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50.发明授权Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化公开(公告)号：US06373289B1
公开(公告)日：2002-04-16
申请号：US09752895
申请日：2000-12-26
申请人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
发明人： Aaron K. Martin , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , Shekhar Y. Borkar
IPC分类号： H03K1900
CPC分类号： H03L7/0812 , H03K5/135 , H04L25/242
摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.
摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。
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