公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

公开(公告)号：US06815290B2

公开(公告)日：2004-11-09

申请号：US10457867

申请日：2003-06-10

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06649473B1

公开(公告)日：2003-11-18

申请号：US10330777

申请日：2002-12-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L21/28273

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract translation: 一种制造闪存的浮动栅极的方法。 在半导体衬底上形成有源区。 在有源区域中依次形成第一绝缘层，第一导电层和掩模层。 去除掩模层的一部分以形成第一开口。 形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。 在第二导电层上形成第二绝缘层以填充第一开口。 进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。 去除第二和第三绝缘层以形成第二开口。 第四绝缘层填充在第二开口中。 除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。

公开(公告)号：US06475894B1

公开(公告)日：2002-11-05

申请号：US10052622

申请日：2002-01-18

Applicant: Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

Inventor： Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

IPC: H01L218247

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.

Abstract translation: 本发明提供一种制造闪速存储器的浮动栅极的方法。 首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。 然后形成栅极氧化物层和第一多晶硅层。 第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。 牺牲绝缘体填充到凹部中。 然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。 在第一多晶硅层的侧壁上形成多晶硅间隔物。 在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。 然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。 最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。 在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。 因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。

公开(公告)号：US5872041A

公开(公告)日：1999-02-16

申请号：US933008

申请日：1997-09-18

Applicant: Ta-Yuan Lee ,  Chi-Hui Lin

Inventor： Ta-Yuan Lee ,  Chi-Hui Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating electrodes of a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming a base insulating layer over the semiconductor substrate; forming a stacked layer, including an insulating layer and a mask layer, over the base insulating layer; defining the stacked layer to form an opening to the base insulating layer; forming a first conducting layer over the stacked layer; forming a spacer on the sidewall of the first conducting layer in the opening; etching the bottom of the opening by using the mask layer and the spacer as a mask to expose a portion of the semiconductor substrate; forming a second conducting layer in the opening to electrically connect the exposed semiconductor substrate; and removing the spacer to leave the first and the second conducting layers as a capacitor electrode.

Abstract translation: 公开了一种在半导体衬底上制造电容器的电极的方法。 该方法包括以下步骤：在半导体衬底上形成基极绝缘层; 在所述基底绝缘层上形成包括绝缘层和掩模层的层叠层; 限定所述堆叠层以形成到所述基底绝缘层的开口; 在堆叠层上形成第一导电层; 在所述开口中的所述第一导电层的侧壁上形成间隔物; 通过使用掩模层和间隔物作为掩模蚀刻开口的底部以暴露半导体衬底的一部分; 在所述开口中形成第二导电层以电连接所暴露的半导体衬底; 并且移除间隔物以将第一和第二导电层留作电容器电极。