公开(公告)号：US07411444B2

公开(公告)日：2008-08-12

申请号：US10712593

申请日：2003-11-13

申请人： Khurram Muhammad ,  Robert B. Staszewski ,  Dirk Leipold

发明人： Khurram Muhammad ,  Robert B. Staszewski ,  Dirk Leipold

IPC分类号： H03K5/00

CPC分类号： H04B1/109 ,  H03H19/004

摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

摘要翻译： 改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。 该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

公开(公告)号：US07356069B2

公开(公告)日：2008-04-08

申请号：US10132624

申请日：2002-04-25

申请人： Khurram Muhammad ,  Carl M. Panasik ,  Dirk Leipold

发明人： Khurram Muhammad ,  Carl M. Panasik ,  Dirk Leipold

IPC分类号： H04B1/707

CPC分类号： H03H15/00 ,  H03H19/004 ,  H04B1/0003 ,  H04B1/0025 ,  H04B1/28 ,  H04L27/24

摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional cycles of the first voltage waveform are obtained. The samples are obtained in response to a control signal indicative of a code used to produce the first voltage waveform, and the samples are combined to produce the second voltage waveform.

摘要翻译： 第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。 响应于指示用于产生第一电压波形的代码的控制信号而获得样本，并且采样被组合以产生第二电压波形。

公开(公告)号：US07057540B2

公开(公告)日：2006-06-06

申请号：US10273217

申请日：2002-10-17

申请人： Khurram Muhammad ,  Robert B. Staszewski ,  Feng Chen ,  Dirk Leipold

发明人： Khurram Muhammad ,  Robert B. Staszewski ,  Feng Chen ,  Dirk Leipold

IPC分类号： H03M3/00

CPC分类号： H03M3/47 ,  H03M3/496 ,  H04B1/1036

摘要： A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.

摘要翻译： Σ-Δ模数转换器 - 具有噪声整形和高频操作等优点。 然而，需要提供具有低噪声特性的高度过采样离散时间采样流所需的采样电路难以设计和实现。 本发明提供了具有这种采样电路310的Σ-Δ混合器300。 本发明公开了一种使用具有低噪声特性的开关电容器307,308和309的采样电路，同时能够提供高度过采样的离散时间采样流。

公开(公告)号：US06959049B2

公开(公告)日：2005-10-25

申请号：US09828338

申请日：2001-04-06

申请人： Robert B. Staszewski ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Dirk Leipold

IPC分类号： H03D7/00 ,  H03D7/12 ,  H03D7/14 ,  H04B1/26 ,  H04B1/28 ,  H03K9/00 ,  H04B1/16 ,  H04L27/08

CPC分类号： H03D7/1441 ,  H03D7/125 ,  H03D7/1466 ,  H03D7/1475 ,  H04B1/28

摘要： A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).

摘要翻译： 多抽头数字脉冲驱动混频器有利地通过将本地振荡器频率（F LO LO）从接收频带中移位来避免本地振荡器（11）的泄漏。 通过使用数字脉冲（51,52）作为混频器驱动信号（16），有利地实现了低噪声系数。

公开(公告)号：US20050195917A1

公开(公告)日：2005-09-08

申请号：US10883501

申请日：2004-06-30

申请人： Robert Staszewski ,  Dirk Leipold

发明人： Robert Staszewski ,  Dirk Leipold

IPC分类号： H04L27/04

CPC分类号： H03J7/047 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L1/00 ,  H03L2207/50

摘要： A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.

摘要翻译： 移动设备包括用于以参考频率的倍数产生频道频率的频率合成器电路。 参考频率由自由运行的晶体振荡器产生，没有频率稳定电路。 通过调整频率合成器的乘法因子来补偿晶体振荡器输出的变化。

公开(公告)号：US20050186920A1

公开(公告)日：2005-08-25

申请号：US11062254

申请日：2005-02-18

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Sameh Rezeq

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Sameh Rezeq

IPC分类号： H03C3/00 ,  H03L7/16 ,  H04B1/04 ,  H04B1/06 ,  H04B1/68

CPC分类号： H03L7/16 ,  H03L2207/50

摘要： A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.

摘要翻译： 一种用于数字RF处理器（DRP）中的噪声和伪噪声抑制的新型装置和方法。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 噪声抑制方案消除了通过电磁，电源，接地和基板路径传输的各种片上干扰源引起的噪声。 噪声抑制方案允许所有数字PLL（ADPLL）以这样的方式操作，以避免产生通常由芯片上的干扰源的注入拉动效应产生的杂散。 频率参考时钟重新定时与RF振荡器时钟同步，用于驱动DRP的整个数字逻辑电路。 这确保了整个系统中不同的时钟沿不会出现相互漂移。 还提出了一种提高ADPLL内数字转换器的分辨率质量的方法。 该方法通过将参考时钟传递通过由Σ-Δ调制器控制的延迟电路来抖动参考时钟。 由于TDC定时估计的不正确的量化，抖动参考时钟降低了对ADPLL输出的相位噪声的影响。

公开(公告)号：US06882829B2

公开(公告)日：2005-04-19

申请号：US10114227

申请日：2002-04-02

申请人： Alexander Mostov ,  Dirk Leipold

发明人： Alexander Mostov ,  Dirk Leipold

IPC分类号： H04B1/04 ,  H04B1/48 ,  H04B1/44

CPC分类号： H04B1/48 ,  H04B1/04

摘要： A novel integrated circuit incorporating a transmit/receive antenna switch capable of being integrated using silicon based RF CMOS semiconductor processes and a power amplifier on the same substrate. The switch circuit is constructed whereby the substrate (i.e. bulk) terminals of the FETs are left floating thus improving the isolation and reducing the insertion loss of the switch. Floating the substrate of the transistors eliminates most of the losses caused by leakage paths through parasitic capacitances internal to the transistor thus improving the isolation and reducing the insertion loss of the switch. Alternatively, the substrate can be connected to the source or to ground via a resistor of sufficiently high value to effectively float the substrate.

摘要翻译： 一种新颖的集成电路，其结合了能够使用硅基RF CMOS半导体工艺集成的发射/接收天线开关和在同一衬底上的功率放大器。 开关电路被构造成使得FET的衬底（即本体）端子悬空，从而改善隔离并降低开关的插入损耗。 浮置晶体管的基板消除了由通过晶体管内部的寄生电容的泄漏路径引起的大部分损耗，从而改善了隔离并降低了开关的插入损耗。 或者，衬底可以通过足够高的电阻器连接到源极或接地，以有效地浮动衬底。

公开(公告)号：US06429693B1

公开(公告)日：2002-08-06

申请号：US09608317

申请日：2000-06-30

申请人： Robert B. Staszewski ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Dirk Leipold

IPC分类号： H03D324

CPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L2207/50

摘要： A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

摘要翻译： 提供数字分数相位检测器以实现频率合成器架构，其自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。 通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。 数字分数相位检测器能够容纳量化方案，以通过使用时间 - 数字转换器来测量VCO输出时钟的显着边缘与参考时钟之间的分数延迟差，以将时差表示为要使用的数字字 由频率合成器。

公开(公告)号：US08855236B2

公开(公告)日：2014-10-07

申请号：US13237740

申请日：2011-09-20

申请人： Robert B. Staszewski ,  Sameh Rezeq ,  Dirk Leipold

发明人： Robert B. Staszewski ,  Sameh Rezeq ,  Dirk Leipold

IPC分类号： H03C1/52 ,  H04L27/36

CPC分类号： H04L27/361

摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.

摘要翻译： 使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。 数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。 用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

公开(公告)号：US08060027B2

公开(公告)日：2011-11-15

申请号：US12721930

申请日：2010-03-11

申请人： Khurram Muhammad ,  Dirk Leipold

发明人： Khurram Muhammad ,  Dirk Leipold

IPC分类号： H04B1/38

CPC分类号： H03C5/00 ,  H04B1/525 ,  H04B1/707

摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

摘要翻译： 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。 此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。