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1.发明申请Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor 审中-公开噪声抑制和抖动的装置和方法，以提高数字RF处理器中的分辨率质量公开(公告)号：US20050186920A1
公开(公告)日：2005-08-25
申请号：US11062254
申请日：2005-02-18
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
CPC分类号： H03L7/16 , H03L2207/50
摘要： A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.
摘要翻译： 一种用于数字RF处理器（DRP）中的噪声和伪噪声抑制的新型装置和方法。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 噪声抑制方案消除了通过电磁，电源，接地和基板路径传输的各种片上干扰源引起的噪声。 噪声抑制方案允许所有数字PLL（ADPLL）以这样的方式操作，以避免产生通常由芯片上的干扰源的注入拉动效应产生的杂散。 频率参考时钟重新定时与RF振荡器时钟同步，用于驱动DRP的整个数字逻辑电路。 这确保了整个系统中不同的时钟沿不会出现相互漂移。 还提出了一种提高ADPLL内数字转换器的分辨率质量的方法。 该方法通过将参考时钟传递通过由Σ-Δ调制器控制的延迟电路来抖动参考时钟。 由于TDC定时估计的不正确的量化，抖动参考时钟降低了对ADPLL输出的相位噪声的影响。
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2.发明申请Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权使用反向时钟的发送缓冲器中的负贡献偏移补偿公开(公告)号：US20070008199A1
公开(公告)日：2007-01-11
申请号：US11178993
申请日：2005-07-11
申请人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
发明人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
IPC分类号： H03M1/06
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译： 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用，反时限与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。
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公开(公告)号：US07623838B2
公开(公告)日：2009-11-24
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。
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4.发明申请Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术公开(公告)号：US20060164160A1
公开(公告)日：2006-07-27
申请号：US11388558
申请日：2006-03-24
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译： 改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。 该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。
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公开(公告)号：US20060290435A1
公开(公告)日：2006-12-28
申请号：US11464420
申请日：2006-08-14
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。
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6.发明申请Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权具有II型全数字锁相环（PLL）的无线通信设备公开(公告)号：US20050212606A1
公开(公告)日：2005-09-29
申请号：US11122670
申请日：2005-05-04
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。
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公开(公告)号：US20050130618A1
公开(公告)日：2005-06-16
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。
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公开(公告)号：US20060135107A1
公开(公告)日：2006-06-22
申请号：US11339386
申请日：2006-01-25
IPC分类号： H04B1/10
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译： 通过反馈消除接近干扰的系统和方法。 优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。 干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。 然后在采样单元中消除干扰源。 另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。
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公开(公告)号：US20050233725A1
公开(公告)日：2005-10-20
申请号：US10828386
申请日：2004-04-20
CPC分类号： H03D7/18 , H03H19/004 , H03H2007/0192
摘要： Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.
摘要翻译： 公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。 公开了在信号处理系统的同相和正交分支中使用旋转电容器。 在I和Q通道的分支之间的信息交换被用于实现复杂的过滤器。 还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。
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10.发明申请Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术公开(公告)号：US20050104654A1
公开(公告)日：2005-05-19
申请号：US10712593
申请日：2003-11-13
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译： 改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。 该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。
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