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    Selective STI stress relaxation through ion implantation
    42.
    发明授权
    Selective STI stress relaxation through ion implantation 有权
    通过离子注入选择性STI应力松弛

    公开(公告)号：US08008744B2

    公开(公告)日：2011-08-30

    申请号：US12790975

    申请日：2010-05-31

    申请人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    发明人： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    IPC分类号： H01L21/36

    CPC分类号： H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

    摘要： A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

    摘要翻译： 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。

    FinFET with novel body contact for multiple Vt applications
    43.
    发明申请
    FinFET with novel body contact for multiple Vt applications 有权
    FinFET具有新的身体接触，适用于多种Vt应用

    公开(公告)号：US20120007180A1

    公开(公告)日：2012-01-12

    申请号：US12803776

    申请日：2010-07-06

    申请人： Chunshan Yin ,  Kian Ming Tan ,  Jae Gon Lee

    发明人： Chunshan Yin ,  Kian Ming Tan ,  Jae Gon Lee

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

    摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。 形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。 在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。 在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。 因此，可以为不同的应用制造具有不同Vt的各种FinFET。

    Method to tune narrow width effect with raised S/D structure
    44.
    发明授权
    Method to tune narrow width effect with raised S/D structure 有权
    用提高的S / D结构调整窄宽度效应的方法

    公开(公告)号：US08785287B2

    公开(公告)日：2014-07-22

    申请号：US12803754

    申请日：2010-07-06

    申请人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    发明人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    IPC分类号： H01L21/336 ,  H01L21/265

    CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/7848

    摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

    摘要翻译： 制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

    Modifying growth rate of a device layer
    45.
    发明授权
    Modifying growth rate of a device layer 有权
    修改设备层的增长速度

    公开(公告)号：US08633081B2

    公开(公告)日：2014-01-21

    申请号：US12980376

    申请日：2010-12-29

    申请人： Chunshan Yin ,  Palanivel Balasubramaniam ,  Jae Gon Lee ,  Elgin Quek

    发明人： Chunshan Yin ,  Palanivel Balasubramaniam ,  Jae Gon Lee ,  Elgin Quek

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/2822 ,  H01L21/76232

    摘要： A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.

    摘要翻译： 一种器件包括具有其上形成有晶体管的器件区域的衬底。 器件区域包括有效边缘区域和具有不同氧化生长速率的活性中心区域。 使用包含修饰氧化生长速率的掺杂剂的生长速率调节剂（GRM）来制造具有均匀厚度的栅极氧化物层。 取决于所使用的掺杂剂的类型，GRM可以增强或延缓氧化生长。 氟掺杂剂增强氧化生长速率，而氮掺杂剂延缓氧化生长速率。

    FinFET with novel body contact for multiple Vt applications
    46.
    发明授权
    FinFET with novel body contact for multiple Vt applications 有权
    FinFET具有新的身体接触，适用于多种Vt应用

    公开(公告)号：US08735984B2

    公开(公告)日：2014-05-27

    申请号：US12803776

    申请日：2010-07-06

    申请人： Chunshan Yin ,  Kian Ming Tan ,  Jae Gon Lee

    发明人： Chunshan Yin ,  Kian Ming Tan ,  Jae Gon Lee

    IPC分类号： H01L21/84 ,  H01L27/12

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

    摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。 形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。 在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。 在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。 因此，可以为不同的应用制造具有不同Vt的各种FinFET。

    Novel method to tune narrow width effect with raised S/D structure
    47.
    发明申请
    Novel method to tune narrow width effect with raised S/D structure 有权
    用提高的S / D结构调整窄宽度效应的新方法

    公开(公告)号：US20120007185A1

    公开(公告)日：2012-01-12

    申请号：US12803754

    申请日：2010-07-06

    申请人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    发明人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/7848

    摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

    摘要翻译： 制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

    ASYNCHRONOUS BRIDGE
    48.
    发明申请
    ASYNCHRONOUS BRIDGE 有权
    异步桥

    公开(公告)号：US20130138848A1

    公开(公告)日：2013-05-30

    申请号：US13617734

    申请日：2012-09-14

    申请人： Bub-Chul Jeong ,  Jae Geun Yun ,  Jae Gon Lee ,  Soo Wan Hong

    发明人： Bub-Chul Jeong ,  Jae Geun Yun ,  Jae Gon Lee ,  Soo Wan Hong

    IPC分类号： G06F13/38

    CPC分类号： G06F13/405

    摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

    摘要翻译： 异步桥包括传输单元和接收单元。 发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入 数据，按读取地址指示。 接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。

    Integrated circuit system employing stress-engineered spacers
    49.
    发明授权
    Integrated circuit system employing stress-engineered spacers 有权
    采用应力工程间隔件的集成电路系统

    公开(公告)号：US08338245B2

    公开(公告)日：2012-12-25

    申请号：US12048994

    申请日：2008-03-14

    申请人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    发明人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

    摘要翻译： 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。