公开(公告)号：US5378647A

公开(公告)日：1995-01-03

申请号：US140404

申请日：1993-10-25

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/112

摘要： The process comprises a sequence of steps initiated by forming a word line mask on the surface of a substrate of a first conductivity type. Ions are implanted to form word lines covered by a dielectric layer. A polysilicon layer doped with a given conductivity type on the dielectric layer is formed on a second dielectric layer on the polysilicon layer. Bit lines are formed with a different conductivity type in the polysilicon layer. Forming a code mask above the polysilicon layer with openings above predetermined regions, etched through the mask to remove predetermined regions in the first polysilicon layer, whereby the ROM is encoded. Preferably, a combined silicon dioxide and silicon nitride layer is formed above the polysilicon layer before forming the code mask. Preferably, the silicon dioxide is deposited first, patterned and used as a mask for forming dopant patterns in the polysilicon layer through openings therein. Preferably, a layer of silicon nitride is deposited upon the silicon dioxide to a greater thickness than the silicon dioxide and is then planarized. Preferably, the dielectric layer formed above the word lines comprises a gate oxide layer.

摘要翻译： 该方法包括通过在第一导电类型的衬底的表面上形成字线掩模来启动的步骤序列。 植入离子以形成由介电层覆盖的字线。 在多晶硅层上的第二介质层上形成在电介质层上掺杂给定导电类型的多晶硅层。 位线在多晶硅层中由不同的导电类型形成。 在多晶硅层之上形成具有高于预定区域的开口的代码掩模，通过掩模蚀刻以除去第一多晶硅层中的预定区域，从而对ROM进行编码。 优选地，在形成代码掩模之前，在多晶硅层的上方形成组合的二氧化硅和氮化硅层。 优选地，首先沉积二氧化硅，构图并用作掩模，以通过其中的开口在多晶硅层中形成掺杂剂图案。 优选地，将氮化硅层沉积在二氧化硅上至比二氧化硅更大的厚度，然后被平坦化。 优选地，形成在字线上方的电介质层包括栅极氧化物层。

公开(公告)号：US20140046728A1

公开(公告)日：2014-02-13

申请号：US14035825

申请日：2013-09-24

申请人： Jason Tryfon ,  Gary Hong

发明人： Jason Tryfon ,  Gary Hong

IPC分类号： G06Q30/02

CPC分类号： G06Q30/0203 ,  G06Q10/107 ,  H04L51/04 ,  H04L51/18 ,  H04L51/38

摘要： Systems and methods for processing alert communications are provided herein. Some exemplary methods may include processing alert communications on a mobile client computing device, where the mobile client computing device having a mobile survey management application. The method may also include executing instructions stored in memory to: capture at least a portion of an electronic mail alert communication provided to the mobile client computing device, the electronic mail alert communication being provided to the mobile client computing device by a survey management application of an application server, to establish an active issue within the mobile survey management application, and provide notification to the survey management application that the active issue has been resolved.

摘要翻译： 本文提供了用于处理警报通信的系统和方法。 一些示例性方法可以包括处理移动客户端计算设备上的警报通信，其中移动客户端计算设备具有移动调查管理应用。 该方法还可以包括执行存储在存储器中的指令以：捕获提供给移动客户端计算设备的电子邮件警报通信的至少一部分，电子邮件警报通信被提供给移动客户端计算设备 应用服务器，在移动调查管理应用程序中建立活动问题，并向调查管理应用程序通知活动问题已经解决。

公开(公告)号：US06281544B1

公开(公告)日：2001-08-28

申请号：US09521984

申请日：2000-03-09

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L2976

CPC分类号： H01L27/11521

摘要： A flash memory structure comprises a first polysilicon layer above a semiconductor substrate; a thin dielectric layer above the first polysilicon layer; and a second polysilicon layer across and above the dielectric layer and the substrate, wherein the second polysilicon layer has a linear shape when viewed from the top. The memory structure further comprises a drain region in the semiconductor substrate on one side of the second polysilicon layer; a trench isolation structure for insulating from neighboring devices; a buried metallic layer located inside a portion of the trench isolation structure close to the upper surface of the substrate; and a common source region located on the other side of the first polysilicon layer just opposite the drain region such that the common source region at least includes a source region and a buried metallic layer alternately linked together.

摘要翻译： 闪存结构包括半导体衬底上方的第一多晶硅层; 在第一多晶硅层上方的薄介电层; 以及在所述电介质层和所述衬底之上和之上的第二多晶硅层，其中当从顶部观察时，所述第二多晶硅层具有线性形状。 存储器结构还包括位于第二多晶硅层一侧的半导体衬底中的漏极区域; 用于与相邻设备绝缘的沟槽隔离结构; 位于所述沟槽隔离结构的靠近所述衬底的上表面的部分内的掩埋金属层; 以及公共源极区域，位于与漏极区域正好相反的第一多晶硅层的另一侧上，使得公共源极区域至少包括交替地连接在一起的源极区域和埋入金属层。

公开(公告)号：US06214667B1

公开(公告)日：2001-04-10

申请号：US09292870

申请日：1999-04-16

申请人： Yen-Lin Ding ,  Gary Hong

发明人： Yen-Lin Ding ,  Gary Hong

IPC分类号： H01L21336

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： An improved method for fabricating a flash memory on a semiconductor substrate is provided. A patterned gate oxide layer and a patterned mask layer are formed on the substrate. Hard material spacers are formed on sidewalls of the gate oxide layer and the mask layer. A shallow trench isolation is formed in the substrate using the mask layer and the hard material spacers as masks. The hard material spacers and the mask layer are removed. A tunneling oxide layer is formed on a portion of the substrate beside the gate oxide layer. A floating gate is formed over the gate oxide layer and the tunneling oxide layer. A dielectric layer is formed over the floating gate. A control gate is formed over the dielectric layer.

摘要翻译： 提供了一种用于在半导体衬底上制造闪速存储器的改进方法。 在衬底上形成图案化的栅极氧化物层和图案化的掩模层。 硬质材料间隔物形成在栅极氧化物层和掩模层的侧壁上。 使用掩模层和硬质材料间隔物作为掩模在衬底中形成浅沟槽隔离。 去除硬质材料间隔物和掩模层。 在栅极氧化物层旁边的衬底的一部分上形成隧道氧化物层。 在栅极氧化物层和隧道氧化物层上形成浮栅。 在浮栅上方形成介电层。 在电介质层上形成控制栅极。

公开(公告)号：US06204113B1

公开(公告)日：2001-03-20

申请号：US08756914

申请日：1996-11-26

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L218242

CPC分类号： H01L27/10852

摘要： A method of forming data storage capacitors in DRAM cells, which data storage capacitors each have an increased surface area for the charge storage plates of the capacitors in order to increase the capacitance. The individual method allows ULSI (Ultra Large Scale Integration) DRAMs, although reduced in circuit element size, to be formed with data storage capacitors having a sufficiently large capacitance to reliably retain electric charges. In this method, a double-trench structure is formed in at least two overlaying conductive layers serving as a bottom plate of the data storage capacitor. A dielectric layer is then formed over the bottom plate, and subsequently, another conductive layer serving as a top plate of the data storage capacitor is formed over the dielectric layer. In this semiconductor structure, the double-trench structure in the data storage capacitor increases the surface area of the bottom plate, thus proportionally increasing the capacitance of the data storage capacitor.

摘要翻译： 在DRAM单元中形成数据存储电容器的方法，其中数据存储电容器各自具有用于电容器的电荷存储板的增加的表面积，以增加电容。 单独的方法允许ULSI（超大规模集成）DRAM尽管电路元件尺寸减小，但是由具有足够大的电容的数据存储电容器形成以可靠地保持电荷。 在该方法中，在用作数据存储电容器的底板的至少两个覆盖导电层中形成双沟槽结构。 然后在底板上形成电介质层，随后在电介质层上形成用作数据存储电容器的顶板的另一导电层。 在该半导体结构中，数据存储电容器中的双沟槽结构增加了底板的表面积，从而成比例地增加了数据存储电容器的电容。

公开(公告)号：US6157057A

公开(公告)日：2000-12-05

申请号：US24782

申请日：1998-02-17

申请人： Yau-Kae Sheu ,  Gary Hong

发明人： Yau-Kae Sheu ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/7885

摘要： A flash memory cell. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

摘要翻译： 闪存单元。 在沟道区域和漏极区域之间形成具有与漏极区域相反极性的重掺杂区域。 重掺杂区域是沿浮动栅极的一侧向漏极和源极区域延伸的棒状。 此外，通过向漏极区域施加零电压并且向源极区域施加非零电压来反向执行读取操作。

公开(公告)号：US6146940A

公开(公告)日：2000-11-14

申请号：US967

申请日：1997-12-30

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/368

CPC分类号： H01L27/10852 ,  H01L21/316 ,  H01L21/76895 ,  H01L27/10873 ,  H01L28/84

摘要： A method of fabricating a dynamic random access memory is disclosed, which mainly utilizing selective liquid-phase deposition process to form an insulation layer on the gate electrode structure.

摘要翻译： 公开了一种制造动态随机存取存储器的方法，其主要利用选择性液相沉积工艺在栅电极结构上形成绝缘层。

公开(公告)号：US6071776A

公开(公告)日：2000-06-06

申请号：US186748

申请日：1998-11-05

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11521

摘要： A method of manufacturing a flash memory structure that also includes the process of forming a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Thereafter, etching is carried out to form a shallow trench within a portion of the shallow trench isolation structure. The shallow trench is formed where a common source terminal is subsequently formed. Next, metallic material is deposited into the trench to form a buried metallic layer. Then, a stacked gate is formed above the semiconductor substrate. Finally, ions are implanted into the substrate on each side of the stacked gate using the stacked gate itself as a mask to form a source region and a drain region. The source region and the buried metallic layer are connected together to form a common source region. The process of forming the buried metallic layer in the substrate not only is compatible with the process of forming a shallow trench isolation structure, but the device so formed also takes up less chip area. Hence, a device array having a higher density can be produced.

摘要翻译： 一种制造闪存结构的方法，其还包括形成浅沟槽隔离结构的工艺。 该方法包括提供半导体衬底，然后在衬底内形成浅沟槽隔离结构的步骤。 此后，进行蚀刻以在浅沟槽隔离结构的一部分内形成浅沟槽。 形成浅沟槽，其中随后形成公共源极端子。 接下来，将金属材料沉积到沟槽中以形成掩埋的金属层。 然后，在半导体基板的上方形成层叠栅极。 最后，使用层叠栅极本身作为掩模将离子注入层叠栅极的每一侧上的衬底中，以形成源区和漏区。 源极区域和埋入金属层连接在一起形成公共源极区域。 在衬底中形成掩埋金属层的过程不仅与形成浅沟槽隔离结构的过程兼容，而且形成的器件也占用较少的芯片面积。 因此，可以制造具有较高密度的器件阵列。

公开(公告)号：US6051479A

公开(公告)日：2000-04-18

申请号：US140114

申请日：1998-08-25

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76235

摘要： A method of forming a shallow trench isolation in a semiconductor substrate. A mask layer is formed to cover an active region of the substrate. A trench is formed within the exposed substrate. The trench is filled with an insulation layer. The dimension of the mask layer is shrunk. A thermal oxidation process is performed to form an oxide protrusion between the trench and the active region. The mask layer is removed.

摘要翻译： 一种在半导体衬底中形成浅沟槽隔离的方法。 形成掩模层以覆盖衬底的有源区。 在暴露的衬底内形成沟槽。 沟槽填充有绝缘层。 掩模层的尺寸缩小。 进行热氧化处理以在沟槽和有源区域之间形成氧化物突起。 去除掩模层。

公开(公告)号：US6037227A

公开(公告)日：2000-03-14

申请号：US950719

申请日：1997-10-15

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A mask ROM uses a bit line structure having a vertically graded dopant distribution or a distinct two level dopant distribution. A bit line might include a highly doped region buried deeply within the substrate that is connected to a comparatively lightly doped region formed above the more highly doped region. The vertical structure of the bit line allows the bit line to be less resistive than the simpler shallow bit line structure conventionally used. The vertical structure (i.e., the two level or graded structure) of the bit line allows the bit line to have a lower doping immediately adjacent the channel region, which reduces the likelihood of punchthrough. The deeper, highly doped portions of the bit line are narrow and laterally confined so that well defined antipunchthrough implantations can be formed which lie between but separated from the more highly doped portions of the bit lines. This aspect of the structure reduces the likelihood of punchthrough while limiting the extent of overlap between the buried bit lines and the antipunchthrough implantation.

摘要翻译： 掩模ROM使用具有垂直渐变掺杂剂分布或不同二级掺杂剂分布的位线结构。 位线可以包括深埋在衬底内的高掺杂区域，其连接到形成在更高掺杂区域上方的相对轻掺杂区域。 位线的垂直结构允许位线比常规使用的较简单的浅位线结构的电阻更小。 位线的垂直结构（即，两级或等级结构）允许位线在沟道区域附近具有较低的掺杂，这降低了穿通的可能性。 位线的较深的，高度掺杂的部分是窄的并且横向受限制，使得可以形成位于但位于比特线的更高掺杂部分之间但与之分开的明确的反穿通注入。 该结构的这个方面减少了穿透的可能性，同时限制了掩埋位线与抗穿透植入之间的重叠程度。