公开(公告)号：US07864760B2

公开(公告)日：2011-01-04

申请号：US10930456

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: H04L12/28

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

公开(公告)号：US20090201935A1

公开(公告)日：2009-08-13

申请号：US12028586

申请日：2008-02-08

Applicant: David T. Hass ,  Kaushik Kuila ,  Ahmed Shahid

Inventor： David T. Hass ,  Kaushik Kuila ,  Ahmed Shahid

IPC: H04L12/56

CPC classification number: H04L69/22 ,  G06F9/30054 ,  G06F9/3836 ,  G06F9/3851 ,  H04L45/00 ,  H04L45/7453 ,  H04L45/7457

Abstract: An apparatus and method are provided for allocating a plurality of packets to different processor threads. In operation, a plurality of packets are parsed to gather packet information. Additionally, a parse operation is performed utilizing the packet information to generate a key, and a hash algorithm is performed on this key to produce a hash. Further, the packets are allocated to different processor threads, utilizing the hash or the key.

Abstract translation: 提供了一种用于将多个分组分配给不同处理器线程的装置和方法。 在操作中，解析多个分组以收集分组信息。 此外，使用分组信息来执行解析操作以生成密钥，并且对该密钥执行散列算法以产生散列。 此外，使用散列或密钥将分组分配给不同的处理器线程。

公开(公告)号：US07538696B2

公开(公告)日：2009-05-26

申请号：US11849166

申请日：2007-08-31

Applicant: Robert William Laker ,  David T. Hass

Inventor： Robert William Laker ,  David T. Hass

IPC: H03M7/34

CPC classification number: H03M7/40 ,  H03M7/3086

Abstract: An apparatus to implement Huffman decoding in an INFLATE process in a compression engine. An embodiment of the apparatus includes a bit buffer, a set of comparators, and a lookup table. The bit buffer stores a portion of a compressed data stream. The set of comparators compares the portion of the compressed data stream with a plurality of predetermined values. The lookup table stores a plurality of LZ77 code segments and outputs one of the LZ77 code segments corresponding to an index at least partially derived from a comparison result from the set of comparators.

Abstract translation: 一种用于在压缩引擎中的INFLATE过程中实现霍夫曼解码的装置。 该装置的实施例包括位缓冲器，一组比较器和查找表。 比特缓冲器存储压缩数据流的一部分。 比较器组将压缩数据流的部分与多个预定值进行比较。 查找表存储多个LZ77代码段，并且输出与至少部分地从比较器组的比较结果导出的索引相对应的LZ77代码段中的一个。

公开(公告)号：US07509462B2

公开(公告)日：2009-03-24

申请号：US10930179

申请日：2004-08-31

Applicant: David T. Hass ,  Ricardo Ramirez

Inventor： David T. Hass ,  Ricardo Ramirez

IPC: G06F12/00 ,  G06F13/00 ,  G06F15/16 ,  H04L12/58

CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20090006510A1

公开(公告)日：2009-01-01

申请号：US11824501

申请日：2007-06-29

Applicant: Robert William Laker ,  David T. Hass

Inventor： Robert William Laker ,  David T. Hass

IPC: G06F7/00

CPC classification number: H03M7/3086

Abstract: An apparatus to implement a deflate process in a compression engine. An embodiment of the apparatus includes a hash table, a dictionary, comparison logic, and encoding logic. The hash table is configured to hash a plurality of characters of an input data stream to provide a hash address. The dictionary is configured to provide a plurality of distance values in parallel based on the hash address. The distance values are stored in the dictionary. The comparison logic is configured to identify a corresponding length for each matching distance value from the plurality of distance values. The encoding logic is configured to encode the longest length and the matching distance value as a portion of a LZ77 code stream.

Abstract translation: 在压缩引擎中实现放气过程的装置。 该装置的实施例包括哈希表，字典，比较逻辑和编码逻辑。 散列表被配置为对输入数据流的多个字符进行散列以提供散列地址。 字典被配置为基于散列地址并行地提供多个距离值。 距离值存储在字典中。 比较逻辑被配置为从多个距离值中识别每个匹配距离值的对应长度。 编码逻辑被配置为将最长长度和匹配距离值编码为LZ77码流的一部分。

公开(公告)号：US07334086B2

公开(公告)日：2008-02-19

申请号：US10898008

申请日：2004-07-23

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: G06F12/00 ,  G06F15/173

CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20050033832A1

公开(公告)日：2005-02-10

申请号：US10930179

申请日：2004-08-31

Applicant: David T. Hass ,  Ricardo Ramirez

Inventor： David T. Hass ,  Ricardo Ramirez

IPC: G06F12/08 ,  H04L12/56 ,  G06F15/177

CPC classification number: H04L45/52 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/62 ,  H04L12/42 ,  H04L49/00 ,  H04L49/15 ,  H04L49/30 ,  H04L49/35

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US09455598B1

公开(公告)日：2016-09-27

申请号：US13164521

申请日：2011-06-20

Applicant: Kaushik Kuila ,  David T. Hass

Inventor： Kaushik Kuila ,  David T. Hass

IPC: G06F3/00 ,  G06F11/30 ,  G06F3/038 ,  H02J13/00 ,  H04L29/06 ,  H04L12/26

CPC classification number: H02J13/0034 ,  G06F3/038 ,  G06F11/3013 ,  H04L43/022 ,  H04L43/026 ,  H04L43/50 ,  H04L47/125 ,  H04L47/34 ,  H04L69/22

Abstract: Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers.

Abstract translation: 公开了一种用于实现网络系统的灵活解析器的方法。 实现了一个微核解析器来处理网络系统中的数据包。 解析器的微核读取数据包头，并在这些数据包和数据包头上执行任何适当编程的任务。 一个或多个高速缓存可以与微核相关联以保持分组报头。

公开(公告)号：US09069564B1

公开(公告)日：2015-06-30

申请号：US13396007

申请日：2012-02-14

Applicant: Abbas Rashid ,  David T. Hass

Inventor： Abbas Rashid ,  David T. Hass

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3802

Abstract: A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.

Abstract translation: 提供了一种用于在多线程系统中执行有效和有效的调度的方法和系统。 提供了调度的动态控制，其中可以为多线程系统中的一些或所有线程分配优先级权重。 采用优先级权重来控制调度器对线程和线程指令的优先级。 每个线程的指令计数与优先权重组合使用，以确定指令被取出并分配给执行单元进行处理的优先次序顺序。

公开(公告)号：US08754681B2

公开(公告)日：2014-06-17

申请号：US13163605

申请日：2011-06-17

Applicant: Julianne J. Zhu ,  David T. Hass

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: H03L7/06

CPC classification number: H03L7/00

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract translation: 描述了一种用于实现时钟管理系统的改进方法。 提供多部分锁相环电路以处理电路的不同时钟需要，其中多部分锁相环电路内的每个锁相环可以将时钟输出馈送到一个或多个除法器电路。 分频器电路可以专用于特定部件。 例如，SoC PLL可以产生时钟输出到专用于为内容地址存储器（CAM）组件提供时钟的SoC分频器。 这种方法允许时钟管理系统有效地生成具有可变电平频率的时钟信号，即使对于具有许多不同功能部分和组件的复杂电路也是如此。