Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch
    1.
    发明授权
    Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch 有权
    片上系统,方法和计算机程序产品,用于使用集中式片上共享存储器交换机传输消息

    公开(公告)号:US08671220B1

    公开(公告)日:2014-03-11

    申请号:US12325050

    申请日:2008-11-28

    IPC分类号: G06F15/167 G06F15/173

    摘要: A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.

    摘要翻译: 提供了片上系统,方法和计算机程序产品,用于使用集中的片上共享存储器交换机来发送消息。 在操作中,从连接在消息收发网络上的多个代理之一发送消息。 消息在中央共享存储交换机处被接收,中央共享存储器交换机与多个代理中的每一个进行通信。 此外,消息从中央共享存储交换机发送到目的地代理,目的地代理是多个代理之一。

    System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor
    2.
    发明授权
    System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor 有权
    用于减少与多核,多线程处理器中的时间戳相关联的延迟的系统和方法

    公开(公告)号:US08549341B2

    公开(公告)日:2013-10-01

    申请号:US12201689

    申请日:2008-08-29

    IPC分类号: G06F1/00

    摘要: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

    摘要翻译: 提供了一种用于减少与多核,多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心,多个用于网络通信的网络接口,以及定时器电路,用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

    Programmable micro-core processors for packet parsing with packet ordering
    6.
    发明授权
    Programmable micro-core processors for packet parsing with packet ordering 有权
    可编程微核处理器,用于使用数据包排序进行数据包解析

    公开(公告)号:US09244798B1

    公开(公告)日:2016-01-26

    申请号:US13164533

    申请日:2011-06-20

    IPC分类号: G06F3/00 G06F11/30 G06F3/038

    摘要: Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.

    摘要翻译: 公开了一种用于实现网络系统的灵活解析器的方法。 实现了一个微核解析器来处理网络系统中的数据包。 解析器的微核读取数据包头,并在这些数据包和数据包头上执行任何适当编程的任务。 一个或多个高速缓存可以与微核相关联以保持分组报头。 依赖列表用于维护由微核处理的数据包的正确排序。

    SYSTEM AND METHOD FOR REDUCING LATENCY ASSOCIATED WITH TIMESTAMPS IN A MULTI-CORE, MULTI-THREADED PROCESSOR
    7.
    发明申请
    SYSTEM AND METHOD FOR REDUCING LATENCY ASSOCIATED WITH TIMESTAMPS IN A MULTI-CORE, MULTI-THREADED PROCESSOR 有权
    用于减少与多核多线程处理器中的时间戳相关的延迟的系统和方法

    公开(公告)号:US20100058101A1

    公开(公告)日:2010-03-04

    申请号:US12201689

    申请日:2008-08-29

    IPC分类号: G06F1/00 H04J3/06

    摘要: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

    摘要翻译: 提供了一种用于减少与多核,多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心,多个用于网络通信的网络接口,以及定时器电路,用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

    SYSTEM AND METHOD FOR PARSING AND ALLOCATING A PLURALITY OF PACKETS TO PROCESSOR CORE THREADS
    8.
    发明申请
    SYSTEM AND METHOD FOR PARSING AND ALLOCATING A PLURALITY OF PACKETS TO PROCESSOR CORE THREADS 有权
    用于分配和分配多个分组的处理器核心线的系统和方法

    公开(公告)号:US20090201935A1

    公开(公告)日:2009-08-13

    申请号:US12028586

    申请日:2008-02-08

    IPC分类号: H04L12/56

    摘要: An apparatus and method are provided for allocating a plurality of packets to different processor threads. In operation, a plurality of packets are parsed to gather packet information. Additionally, a parse operation is performed utilizing the packet information to generate a key, and a hash algorithm is performed on this key to produce a hash. Further, the packets are allocated to different processor threads, utilizing the hash or the key.

    摘要翻译: 提供了一种用于将多个分组分配给不同处理器线程的装置和方法。 在操作中,解析多个分组以收集分组信息。 此外,使用分组信息来执行解析操作以生成密钥,并且对该密钥执行散列算法以产生散列。 此外,使用散列或密钥将分组分配给不同的处理器线程。

    System and method for offloading packet protocol encapsulation from software
    10.
    发明授权
    System and method for offloading packet protocol encapsulation from software 失效
    从软件卸载数据包协议封装的系统和方法

    公开(公告)号:US08724657B2

    公开(公告)日:2014-05-13

    申请号:US13205420

    申请日:2011-08-08

    IPC分类号: H04J3/24 H04L12/56

    摘要: A method and system of packet assembly is provided. The method includes providing a first packet descriptor. The first packet descriptor is a pointer-to-pointer (P2P) descriptor that includes pointer information. The method further includes retrieving a first pointer referenced by the pointer information of the first packet descriptor; providing the first pointer to a DMA engine; and using the DMA engine to retrieve packet data referenced by the first pointer.

    摘要翻译: 提供了一种分组组装的方法和系统。 该方法包括提供第一分组描述符。 第一个分组描述符是包括指针信息的指针指针(P2P)描述符。 该方法还包括:检索由第一分组描述符的指针信息引用的第一指针; 提供第一个指向DMA引擎的指针; 并使用DMA引擎来检索由第一个指针引用的数据包数据。