公开(公告)号：US07074660B2

公开(公告)日：2006-07-11

申请号：US10765910

申请日：2004-01-29

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is caused to recede by means of a nonlithographic process from contact trenches, which define the contact structures, before the formation of the contact structures. A distance a between the gate electrode and the contact structures is not subject to any tolerances due to the overlay of two independent lithographic masks. For a given extent of the gate electrode along the transistor fin, it is possible to minimize a distance A between the contact structures and thereby significantly increase the packing density of a plurality of fin field-effect transistors on a substrate compared with conventional devices.

Abstract translation: 翅片场效应晶体管的晶体管鳍片布置在两个接触结构之间。 在形成接触结构之前，通过非平版印刷工艺，从形成接触结构的接触沟槽中，将晶体管鳍片封装在三面上的栅电极被后退。 门电极和接触结构之间的距离a由于两个独立的光刻掩模的覆盖而不受任何公差的影响。 对于沿着晶体管鳍片的给定范围的栅电极，可以使接触结构之间的距离A最小化，从而与常规器件相比，显着增加了衬底上的多个鳍状场效应晶体管的堆积密度。

公开(公告)号：US07005346B2

公开(公告)日：2006-02-28

申请号：US10850960

申请日：2004-05-21

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/336

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/1087

Abstract: A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.

Abstract translation: 存储单元具有垂直构造的电容器和布置在其上方的垂直FET，其可以以较低的开销和技术上更可靠的方式产生。 这是通过在半导体衬底中蚀刻平行且具有第一深度的两个第一沟槽来实现的。 在沟槽之间形成网状物，该网状物在其窄边连接到半导体衬底，并且在其下侧被切断并与半导体衬底分离。 然后，悬挂的网带有封闭的电介质。 填充后，施加FET并将其连接到作为存储器节点的网。

公开(公告)号：US07005240B2

公开(公告)日：2006-02-28

申请号：US10370857

申请日：2003-02-20

Applicant: Dirk Manger ,  Matthias Goldbach

Inventor： Dirk Manger ,  Matthias Goldbach

IPC: G03C5/00

CPC classification number: H01L21/0337

Abstract: A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches—for instance for trench capacitors—the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

Abstract translation: 由间隔结构产生硬掩模。 间隔结构由在投影过程中光刻生成的升高结构上的共形沉积形成。 在升高的结构上横向蚀刻共形沉积物，导致间隔物结构。 间隔结构之间的升高的结构随后被蚀刻掉，使得间隔结构保持隔离的方式作为具有双重结构密度的硬掩模的亚光刻结构，与原始在光刻投影中产生的结合密度相比较。 在用于形成沟槽的硬掩模中的例如用于沟槽电容器的规则排列的二维结构阵列中，该方法实现阵列中结构密度的加倍。 通过在第一和第二间隔结构上形成另外的间隔结构形成另外的迭代步骤，从而在硬掩模中实现甚至更高的结构密度增加。

公开(公告)号：US06932916B2

公开(公告)日：2005-08-23

申请号：US10425179

申请日：2003-04-29

Applicant: Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

Inventor： Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  B44C1/22 ,  H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/3083 ,  H01L21/76229 ,  H01L27/1087 ,  H01L29/66181

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract translation: 在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。 第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。 在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。 当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。