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公开(公告)号：US08747680B1
公开(公告)日：2014-06-10
申请号：US13830082
申请日：2013-03-14
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Sanjeev Aggarwal
IPC: B44C1/22
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.
Abstract translation: 一种制造具有在第一导电层和第二导电层之间形成的磁性材料层的基于磁阻的器件的方法，所述磁性材料层包括在第一磁性材料层和第二磁性材料层之间形成的隧道势垒层， 包括去除未被第一硬掩模保护的第一导电层和第一磁性材料层，分别形成第一电极和第一磁性材料; 以及去除不受第二硬掩模保护的隧道势垒层，第二磁性材料层和第二导电层，以形成隧道势垒，第二磁性材料和第二电极。
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公开(公告)号：US11335728B2
公开(公告)日：2022-05-17
申请号：US16881958
申请日：2020-05-22
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Thomas Andre , Sarin A. Deshpande
Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US11189785B2
公开(公告)日：2021-11-30
申请号：US16845405
申请日：2020-04-10
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Kerry Joseph Nagel , Chaitanya Mudivarthi , Sanjeev Aggarwal
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US10950657B2
公开(公告)日：2021-03-16
申请号：US16183956
申请日：2018-11-08
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Sarin A. Deshpande
Abstract: An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD).
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公开(公告)号：US10886463B2
公开(公告)日：2021-01-05
申请号：US16881151
申请日：2020-05-22
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Sarin A. Deshpande
Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
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Patent Agency Ranking
公开(公告)号：US10700123B2
公开(公告)日：2020-06-30
申请号：US16143088
申请日：2018-09-26
Applicant: Everspin Technologies, Inc.
Inventor： Thomas Andre , Sanjeev Aggarwal , Kerry Joseph Nagel , Sarin A. Deshpande
Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号：US10658576B2
公开(公告)日：2020-05-19
申请号：US16580025
申请日：2019-09-24
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Kerry Joseph Nagel , Chaitanya Mudivarthi , Sanjeev Aggarwal
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US20180158498A1
公开(公告)日：2018-06-07
申请号：US15831736
申请日：2017-12-05
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Sanjeev AGGARWAL , Sarin A. Deshpande , Jon Slaughter
Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.
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公开(公告)号：US20180145248A1
公开(公告)日：2018-05-24
申请号：US15855984
申请日：2017-12-27
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Sanjeev Aggarwal , Kerry Joseph Nagel
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
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公开(公告)号：US20180033959A1
公开(公告)日：2018-02-01
申请号：US15727905
申请日：2017-10-09
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Kerry Joseph Nagel , Chaitanya Mudivarthi , Sanjeev Aggarwal
Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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