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    METHOD OF FABRICATING A MAGNETORESISTIVE BIT FROM A MAGNETORESISTIVE STACK
    2.
    发明申请
    METHOD OF FABRICATING A MAGNETORESISTIVE BIT FROM A MAGNETORESISTIVE STACK 有权

    公开(公告)号：US20210119118A1

    公开(公告)日：2021-04-22

    申请号：US17109318

    申请日：2020-12-02

    Applicant: Everspin Technologies, Inc.

    Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

    IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

    METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS
    5.
    发明申请
    METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS 有权

    公开(公告)号：US20250160216A1

    公开(公告)日：2025-05-15

    申请号：US19023944

    申请日：2025-01-16

    Applicant: Everspin Technologies, Inc.

    Inventor： Sanjeev AGGARWAL ,  Sarin A. DESHPANDE ,  Kerry Joseph NAGEL

    IPC: H10N50/01 ,  H10B61/00

    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

    MAGNETORESISTIVE DEVICES AND METHODS OF FABRICATING MAGNETORESISTIVE DEVICES
    6.
    发明申请
    MAGNETORESISTIVE DEVICES AND METHODS OF FABRICATING MAGNETORESISTIVE DEVICES 有权

    公开(公告)号：US20250031580A1

    公开(公告)日：2025-01-23

    申请号：US18776578

    申请日：2024-07-18

    Applicant: Everspin Technologies, Inc.

    Inventor： Kerry Joseph NAGEL ,  SHIMON ,  Sanjeev AGGARWAL

    IPC: H10N50/01 ,  H10N50/10

    Abstract: A method of manufacturing a magnetoresistive device may comprise providing a magnetoresistive structure comprising a bottom electrode, a magnetoresistive stack, and a top electrode. The method may include removing at least a portion of the top electrode using a first etch, where the first etch is performed in the presence of a first gas mixture. Methods of manufacturing the magnetoresistive device may include removing at least a portion of the magnetoresistive stack and the bottom electrode using a second etch, wherein the second etch is performed in the presence of a second gas mixture. The first and second gas mixture may comprise a hydrocarbon including a carbon-carbon double bond or a carbon-carbon triple bond.

    MAGNETORESISTIVE STACK/STRUCTURE AND METHOD OF MANUFACTURING SAME
    7.
    发明公开
    MAGNETORESISTIVE STACK/STRUCTURE AND METHOD OF MANUFACTURING SAME 审中-公开

    公开(公告)号：US20230403943A1

    公开(公告)日：2023-12-14

    申请号：US18456293

    申请日：2023-08-25

    Applicant: Everspin Technologies, Inc.

    Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

    IPC: H10N50/01 ,  H10N50/10

    CPC classification number: H10N50/01 ,  H10N50/10

    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

    METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES
    9.
    发明申请
    METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220336734A1

    公开(公告)日：2022-10-20

    申请号：US17659234

    申请日：2022-04-14

    Applicant: Everspin Technologies, Inc.

    Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Santosh KARRE

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

    Abstract: A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.

    METHODS OF FORMING MAGNETORESISTIVE DEVICES AND INTEGRATED CIRCUITS
    10.
    发明申请
    METHODS OF FORMING MAGNETORESISTIVE DEVICES AND INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200286950A1

    公开(公告)日：2020-09-10

    申请号：US16881958

    申请日：2020-05-22

    Applicant: Everspin Technologies, Inc.

    Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

    IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

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