公开(公告)号：US07208986B2

公开(公告)日：2007-04-24

申请号：US11293634

申请日：2005-12-02

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03L7/00

CPC classification number: H03L7/0812

Abstract: Measure-controlled delay (MCD) circuits are provided for synchronizing an output clock to an input clock. In response to triggering of a measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. Clock synchronization circuits with improved response to process, voltage and temperature (PVT) variations are also provided.

Abstract translation: 提供了测量控制延迟（MCD）电路，用于将输出时钟同步到输入时钟。 响应于测量电路的触发，采样电路对测量延迟阵列的输出进行采样。 当预定的一个或多个采样中的任一个对应于特定逻辑值（即，逻辑“1”或“0”）时，采样复位逻辑防止输出时钟的输出。 例如，当从测量延迟阵列的最早采样点采样的样本对应于逻辑“1”时，采样复位逻辑可以防止MCD电路提供输出时钟。 然后，MCD电路可以响应于从最早采样点采集的样本为逻辑“0”的后续触发来提供输出时钟。 从而降低了输出时钟的相位误差。 还提供了具有对过程，电压和温度（PVT）变化的响应的时钟同步电路。

公开(公告)号：US20070033464A1

公开(公告)日：2007-02-08

申请号：US11183947

申请日：2005-07-18

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G01R31/28

CPC classification number: G11C29/02 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  H03L7/0814

Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract translation: 提供了一种用于将三个产生的时钟信号的相位特性与原始时钟信号进行比较的系统，每个时钟信号与原始时钟信号具有唯一的相位关系，并且基于三个信号的相位特性的接近来选择信号 到原来的信号。 当尝试将内部时钟与外部时钟同步时，选择最接近原来的时钟信号可显着减少锁定时间。 此外，提供了一种用于将三个时钟信号与原始时钟信号进行比较的方法，并且从三个时钟信号中选择与原始时钟信号大致同相的一个。

公开(公告)号：US20070014445A1

公开(公告)日：2007-01-18

申请号：US11152653

申请日：2005-06-14

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G06K9/00 ,  A61B8/00

CPC classification number: G03B42/06 ,  A61B8/00 ,  A61B8/08 ,  A61B8/5276

Abstract: Certain embodiments of the present invention provide a method and system for real-time motion correction in compound ultrasound imaging. Certain embodiments include receiving an image frame, estimating motion between the image frame and a previous image frame, updating a previous motion estimate with the estimated motion to form an updated motion estimate, and correcting the image frame and the previous image frame using the updated motion estimate. The method may also include forming a compound image from the image frames. In an embodiment, motion may be estimated between the image frame and a previous frame using cross correlation, reference point registration, and/or other estimation method, for example. The image frame and the previous image frame may be corrected using the updated motion estimate in an affine transformation or other correction method, for example. In an embodiment, the method provides real-time correction as image frames are being received.

Abstract translation: 本发明的某些实施例提供了一种用于复合超声成像中的实时运动校正的方法和系统。 某些实施例包括接收图像帧，估计图像帧与先前图像帧之间的运动，用所估计的运动更新先前的运动估计，以形成更新的运动估计，以及使用更新的运动来校正图像帧和先前的图像帧 估计。 该方法还可以包括从图像帧形成复合图像。 在一个实施例中，例如，可以使用互相关，参考点注册和/或其他估计方法在图像帧和先前帧之间估计运动。 例如，可以使用仿射变换或其他校正方法中的更新的运动估计来校正图像帧和先前图像帧。 在一个实施例中，当正在接收图像帧时，该方法提供实时校正。

公开(公告)号：US20070013450A1

公开(公告)日：2007-01-18

申请号：US11524842

申请日：2006-09-21

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/089

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract translation: 本发明提供一种降低噪声的方法和装置。 该装置包括相位检测器，其适于确定第一和第二信号之间的相位差，适于基于所确定的相位差产生控制信号的第一电路和第二电路。 第二电路适于接收第三信号，接收第四信号，基于控制信号修改第四信号，并将第三信号和修改的第四信号提供给相位检测器作为第一和第二信号。

公开(公告)号：US07161391B2

公开(公告)日：2007-01-09

申请号：US11003117

申请日：2004-12-03

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G01R25/00

CPC classification number: H03D13/004

Abstract: A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that may result from clock skew and duty cycle distortion. If the condition is detected, an adjusted signal is generated and the adjusted signal is synchronized with the reference signal. By using the generated signal to provide a lock if certain conditions arise, adjustment errors resulting from duty cycle distortion and clock skew can be minimized.

Abstract translation: 提供了一个容错数字相位检测器。 具体地，在数字相位检测器中提供检测器以检测可能由时钟偏移和占空比失真引起的某些故障状况。 如果检测到条件，则生成调整后的信号，调整后的信号与参考信号同步。 通过使用产生的信号来提供锁定，如果出现某些情况，可以将由占空比失真和时钟偏移引起的调整误差降到最小。

公开(公告)号：US07129738B2

公开(公告)日：2006-10-31

申请号：US10379006

申请日：2003-03-04

Applicant: Feng Lin ,  Brian Johnson

Inventor： Feng Lin ,  Brian Johnson

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

Abstract translation: 本发明提供了一种用于校准集成电路器件中的驱动器阻抗的方法和装置。 该方法包括提供来自指示驱动器电路和负载之间的阻抗失配的来自同步电路的信号。 该方法还包括选择驱动器电路的多个阻抗中的一个以减少响应于该信号的阻抗失配。

公开(公告)号：US20060216349A1

公开(公告)日：2006-09-28

申请号：US11423550

申请日：2006-06-12

Applicant: Frank Bunick ,  Feng Lin

Inventor： Frank Bunick ,  Feng Lin

IPC: A61K9/20 ,  A61K31/192 ,  A61K9/68

CPC classification number: A61K9/5047 ,  A61K9/0056 ,  A61K9/2013 ,  A61K31/192 ,  A61K47/12 ,  Y10S514/974

Abstract: Fumaric acid is added in amounts sufficient to reduce the burn sensation commonly associated with propionic acid derivatives.

Abstract translation: 富马酸的添加量足以减少通常与丙酸衍生物相关的烧伤感。

公开(公告)号：US07078053B2

公开(公告)日：2006-07-18

申请号：US10635069

申请日：2003-08-05

Applicant: Frank J. Bunick ,  Feng Lin

Inventor： Frank J. Bunick ,  Feng Lin

IPC: A61K9/28

CPC classification number: A61K9/5047 ,  A61K9/0056 ,  A61K9/2013 ,  A61K31/192 ,  A61K47/12 ,  Y10S514/974

Abstract: Fumaric acid is added in amounts sufficient to reduce the burn sensation commonly associated with propionic acid derivatives.

公开(公告)号：US07020794B2

公开(公告)日：2006-03-28

申请号：US11080678

申请日：2005-03-14

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G06F1/12

CPC classification number: G06F1/10 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0998 ,  Y10T307/951

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

公开(公告)号：US20060058670A1

公开(公告)日：2006-03-16

申请号：US10915177

申请日：2004-08-10

Applicant: Feng Lin ,  Qian Adams

Inventor： Feng Lin ,  Qian Adams

IPC: A61B8/06 ,  A61B8/12

CPC classification number: G03B42/06 ,  G01S7/52047 ,  G01S15/8915 ,  G01S15/8995

Abstract: A method and apparatus for ultrasound spatial compounding imaging with adjustable aperture controls is disclosed. The method and apparatus can improve the image quality of all frames by applying different aperture controls on each frame of the spatially compounded image. One or both of transmit and receive aperture controls may include preventing some element of the transducer array from transmitting or receiving, calculating weighting apodizations to combine with standard apodizations for each frame, or determining an aperture size based on an f-number for the transducer array for each frame.

Abstract translation: 公开了一种用于具有可调孔径控制的超声空间复合成像的方法和装置。 该方法和装置可以通过在空间复合图像的每个帧上应用不同的光圈控制来提高所有帧的图像质量。 发射和接收孔径控制中的一个或两个可以包括防止换能器阵列的一些元件发射或接收，计算加权变迹以与每个帧的标准变迹组合，或者基于换能器阵列的f数来确定孔径尺寸 对于每一帧。