公开(公告)号：US09147028B2

公开(公告)日：2015-09-29

申请号：US13902395

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Lei Yuan

IPC: G06F17/50 ,  H01L29/66 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  Y02T10/82

Abstract: Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder.

Abstract translation: 公开了用于容纳用于半导体单元的单元高度的M2间距的非整数倍的方法以及所得到的器件。 实施例可以包括在具有第一整数和余数乘以金属轨道层的轨道间距的集成电路（IC）内形成单元，以及在金属轨道层的边界处形成用于为 余。

公开(公告)号：US09122830B2

公开(公告)日：2015-09-01

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20150243515A1

公开(公告)日：2015-08-27

申请号：US14186396

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/306 ,  G06F17/50

CPC classification number: H01L21/3088 ,  G03F1/70 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Abstract translation: 一种涉及识别用于构图线型特征的整体目标切割掩模的图案的方法，所述线型特征包括具有内凹角的目标非矩形开口特征，将总体目标切割掩模图案分解为第一和第二子图， 目标图案，其中所述第一子目标图案包括与所述目标非矩形开口特征和所述第二子目标图案的第一部分但不是全部相对应的第一矩形开口特征，所述第一子目标图案包括第二矩形开口特征， 特征对应于目标非矩形开口特征的第二部分但不是全部，第一和第二开口与内凹角相邻重叠，并且生成对应于第一和第二子图的第一和第二组掩模数据， 目标图案，其中基于所识别的切割线间距规则，生成第一组和第二组掩模数据中的至少一个。

公开(公告)号：US08966412B1

公开(公告)日：2015-02-24

申请号：US14035329

申请日：2013-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70283 ,  G03F7/70466

Abstract: One method disclosed herein involves, among other things, identifying a plurality of features within an overall pattern layout that cannot be decomposed using the SADP process, wherein at least first and second adjacent features are required to be same-color features, decreasing a spacing between the first and second adjacent features such that the first feature and the second feature become different-color features so as to thereby render the plurality of features decomposable using the SADP process, decomposing the overall pattern layout into a mandrel mask pattern and a block mask pattern, and generating mask data sets corresponding to the mandrel mask pattern and the block mask pattern.

Abstract translation: 本文公开的一种方法除其他外包括识别不能使用SADP过程分解的整体图案布局中的多个特征，其中至少第一和第二相邻特征需要是相同颜色的特征， 所述第一和第二相邻特征使得所述第一特征和所述第二特征变为不同颜色特征，从而使得所述多个特征可以使用所述SADP处理分解，将所述整体图案布局分解为心轴掩模图案和块掩模图案 并且生成与心轴掩模图案和块掩模图案相对应的掩模数据集。

公开(公告)号：US08918746B1

公开(公告)日：2014-12-23

申请号：US14018074

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G01N23/00 ,  G03F1/00 ,  H01L21/00

CPC classification number: H01L27/0207

Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Abstract translation: 公开了能够选择设计规则以提高IC设计的特征密度的方法和装置。 实施例包括：确定与IC设计的光栅图案重叠的特征，所述光栅图案包括多个光栅结构; 确定与所述光栅图案重叠的切割图案的形状; 以及基于所确定的形状来选择所述特征的多个规则中的一个。

公开(公告)号：US20140353842A1

公开(公告)日：2014-12-04

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处连接到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20140208285A1

公开(公告)日：2014-07-24

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jongwook Kye ,  Harry J. Levinson ,  Jason E. Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。

公开(公告)号：US08789000B1

公开(公告)日：2014-07-22

申请号：US13863591

申请日：2013-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Lei Yuan ,  Jongwook Kye ,  Suresh Venkatesan

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A system and design methodology for performing routing in an integrated circuit design is disclosed. An integrated circuit design is first created using standard cells having metal level 2 (M2) power rails. Routing is performed and power rail current density for the integrated circuit is computed. Standard cells that have power rail current density below a predetermined threshold are replaced with a functionally equivalent standard cell that does not have M2 power rails, and the routing operation is performed again, until the design converges.

Abstract translation: 公开了一种用于在集成电路设计中执行路由的系统和设计方法。 首先使用具有金属级2（M2）电源轨的标准单元创建集成电路设计。 执行路由，并计算集成电路的电源轨电流密度。 具有低于预定阈值的电力轨电流密度的标准电池被替换为不具有M2电力轨的功能等效的标准单元，并且直到设计收敛为止，再次执行路由操作。

公开(公告)号：US11205033B2

公开(公告)日：2021-12-21

申请号：US17070708

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim

IPC: G06F7/50 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  G06F30/394 ,  G06F119/06

Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.

公开(公告)号：US10290582B2

公开(公告)日：2019-05-14

申请号：US15473371

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  G06F17/50 ,  H01L23/528 ,  H01L21/027 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L49/02

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.