-
41.发明授权SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same 有权使用拉伸应力应变膜的SRAM器件及其制造方法公开(公告)号：US07060549B1
公开(公告)日：2006-06-13
申请号：US11174400
申请日：2005-07-01
申请人： Mark Craig , Karsten Wieczorek , Manfred Horstmann
发明人： Mark Craig , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L27/11 , H01L27/1104 , H01L29/78
摘要： SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.
摘要翻译： 提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。 在一个实施例中，SRAM器件包括电耦合和物理隔离的NFET和PFET。 PFET具有栅极区域，源极区域和漏极区域。 拉伸应变应力膜设置在栅极区域和PFET的源极区域和漏极区域的至少一部分上。 用于制造SRAM器件的单元的方法包括制造覆盖衬底的NFET和PFET。 PFET和NFET电耦合并且物理隔离。 在栅极区域和PFET的源极区域和漏极区域的至少一部分上沉积拉伸应变膜。
-
公开(公告)号：US06754553B2
公开(公告)日：2004-06-22
申请号：US09820033
申请日：2001-03-28
IPC分类号： G06F1900
CPC分类号： H01L22/10 , H01J2237/30433 , H01J2237/31701 , H01L21/26506 , H01L21/2658
摘要： Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.
摘要翻译： 测试晶片消耗是半导体工业制造总体成本的重要因素，因为在一次监测植入参数之后报废测试晶片。 本发明提供一种重复使用相同测试晶片多于一次来监测注入参数的方法。 该方法包括以相同的植入和退火条件以及植入各种植入物种以及不同的植入和退火条件一起植入相同植入物种的可能性。 因此，本发明有助于显着减少在植入区域中消耗的测试晶片的数量。
-
43.发明授权Semiconductor device having a low resistance gate conductor and method of fabrication the same 有权具有低电阻栅极导体的半导体器件及其制造方法公开(公告)号：US06281086B1
公开(公告)日：2001-08-28
申请号：US09422548
申请日：1999-10-21
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28105 , H01L29/4966
摘要： A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by providing a conductive layer enclosing the gate electrode so as to significantly increase the surface portion of the gate electrode having a low electric resistance. For example, providing a substantially inverted U-shaped silicide layer enclosing the gate electrode leads to a decrease in the electrical resistance of about 67% with a given aspect ratio of about 1. Moreover, reducing the gate length, i.e., increasing the aspect ratio of the gate electrode results in a nearly complete independence of the gate resistance from the gate length.
摘要翻译： 提供一种半导体器件及其制造方法，其中与常规半导体器件相比，半导体器件表现出较低的栅极延迟时间。 栅极延迟时间的减小通过提供包围栅电极的导电层来显着增加具有低电阻的栅电极的表面部分来实现。 例如，提供围绕栅电极的大致倒U形硅化物层导致电阻降低约67％，给定的纵横比约为1.此外，减小栅极长度，即增加纵横比 的栅电极导致栅极电阻几乎完全独立于栅极长度。
-
44.发明授权Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction 有权通过修改寄生PN结来减少清洁过程中CMOS器件栅极缺陷的方法公开(公告)号：US08039338B2
公开(公告)日：2011-10-18
申请号：US12397574
申请日：2009-03-04
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823871
摘要： By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
摘要翻译： 通过在对栅电极结构进行构图之前将氮掺入P掺杂区域和栅极电极材料的N掺杂区域中，可以显着降低由于反应性湿化学清洗过程引起的屈服损失。
-
45.发明申请CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure 失效CMOS栅极结构包括具有改善的掺杂剂分布均匀性的预制半导体栅极材料和形成该结构的方法公开(公告)号：US20060094183A1
公开(公告)日：2006-05-04
申请号：US11154878
申请日：2005-06-16
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.
摘要翻译： 通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。 掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。
-
46.发明授权Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer 失效使用掺杂的高k电介质层形成场效应晶体管的漏极/源延伸结构的方法公开(公告)号：US06849516B2
公开(公告)日：2005-02-01
申请号：US10442745
申请日：2003-05-21
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.
摘要翻译： 根据本发明的一个说明性实施例，形成场效应晶体管的方法包括在包括在有源区上形成并由栅极绝缘层分离的栅电极的衬底上形成掺杂的高k电介质层。 用衬底进行热处理以将掺杂剂从高k电介质层扩散到活性区域中以形成延伸区域。 图案化高k电介质层以在栅电极的侧壁处形成侧壁间隔物，并且以侧壁间隔物作为注入掩模进行注入工艺以形成源区和漏区。
-
公开(公告)号：US06555892B2
公开(公告)日：2003-04-29
申请号：US09812372
申请日：2001-03-20
IPC分类号： H01L2900
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/76801 , H01L23/5329 , H01L29/41725 , H01L29/41775 , H01L29/4983 , H01L2924/0002 , H01L2924/00
摘要： A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.
-
48.发明授权公开(公告)号：US06274894B1
公开(公告)日：2001-08-14
申请号：US09375920
申请日：1999-08-17
IPC分类号： H01L31072
CPC分类号： H01L29/0847 , H01L29/1083 , H01L29/165 , H01L29/41766 , H01L29/66477 , H01L29/66628 , H01L29/66636
摘要： A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides with oxide or another dielectric for protection during subsequent processing. Anisotropic etching is used to form shallow trenches in the substrate on either side of the gate conductor. The trenches are bounded by the dielectric-coated gate conductor and by dielectric isolation regions, or by an adjacent gate conductor in the case of non-isolated transistors. A selective epitaxy technique may then be used to grow a layer within each trench of a material having a bandgap lower than that of the semiconductor substrate. The lower-bandgap material is preferably grown only on the exposed semiconductor surfaces in the trenches, and not on the surrounding dielectric regions. The lower-bandgap material may be an undoped layer used as a buffer for interdiffusion of dopants between the channel and source/drain regions of the transistor. The lower-bandgap material may also be a heavily doped layer with the same carrier type as the semiconductor substrate, used as a halo region to reduce punchthrough and threshold voltage lowering effects. The buffer and halo functions may also be combined using multilayer source/drain structures. The portion of the trench above such buffer and/or halo layers is filled with a semiconductor material doped with the opposite carrier type than that of the substrate to form lightly-doped-drain portions of the transistor source and drain.
摘要翻译： 提供具有包括低带隙部分的源极和漏极区域的晶体管及其制造方法。 在半导体衬底上的栅极电介质上形成栅极导体。 栅极导体在所有侧面都被氧化物或另一个电介质覆盖，用于在后续处理过程中进行保护。 各向异性蚀刻用于在栅极导体两侧的衬底中形成浅沟槽。 在非隔离晶体管的情况下，沟槽由电介质涂覆的栅极导体和介电隔离区域或相邻栅极导体限制。 然后可以使用选择性外延技术来在具有比半导体衬底的带隙低的带隙的材料的每个沟槽内生长层。 较低带隙材料优选仅在沟槽中的暴露的半导体表面上生长，而不是在周围的电介质区域上生长。 低带隙材料可以是用作缓冲器的未掺杂层，用于在晶体管的沟道和源极/漏极区之间的掺杂剂的相互扩散。 较低带隙材料也可以是具有与半导体衬底相同载流子类型的重掺杂层，用作卤素区域以减少穿通和阈值电压降低效应。 缓冲区和晕圈功能也可以使用多层源/漏结构组合。 在这种缓冲区和/或晕圈之上的沟槽部分填充掺杂有与衬底相反的载体类型的半导体材料，以形成晶体管源极和漏极的轻掺杂漏极部分。
-
49.发明授权Method of forming a gate structure of a transistor by means of scalable spacer technology 失效通过可扩展间隔技术形成晶体管栅极结构的方法公开(公告)号：US06255182B1
公开(公告)日：2001-07-03
申请号：US09503634
申请日：2000-02-14
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , H01L29/665 , H01L29/6659
摘要： A method is described which can be used to form gate structures of very small dimensions in a semiconductor device. The method may be used to avoid employment of highly-sophisticated and cost-intensive DUV photolithography. In one illustrative embodiment, the method comprises forming a gate electrode layer, forming a first mask layer above the gate electrode layer, and forming a sidewall spacer adjacent the sidewalls of the first mask layer. Thereafter, the method comprises forming a second mask layer above a portion of the sidewall spacer and the first mask layer, removing portions of the sidewall spacer to define a hard mask comprised of a portion of the sidewall spacer, and patterning the gate electrode layer using the hard mask to define a gate electrode of the device.
摘要翻译： 描述了可用于在半导体器件中形成非常小尺寸的栅极结构的方法。 该方法可以用于避免使用高度复杂和成本高的DUV光刻。 在一个说明性实施例中，该方法包括形成栅极电极层，在栅极电极层上形成第一掩模层，以及形成邻近第一掩模层的侧壁的侧壁间隔物。 此后，该方法包括在侧壁间隔物和第一掩模层的一部分上方形成第二掩模层，去除侧壁间隔物的部分以限定由侧壁间隔物的一部分组成的硬掩模，并且使用 硬掩模来定义器件的栅电极。
-
公开(公告)号：US06207563B1
公开(公告)日：2001-03-27
申请号：US09245815
申请日：1999-02-05
IPC分类号： H01L2144
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843
摘要： Methods of fabricating a silicide layer on a substrate or transistor structures thereon are provided. An exemplary method includes the steps of depositing a layer of metal on a substrate that has a pn junction. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer. Any unreacted metal is removed. The substrate and the silicide layer are heated above the agglomeration threshold temperature of any filaments of the silicide layer penetrating the pn junction but below the agglomeration threshold temperature of the silicide layer. The method eliminates silicide filaments, particularly in cobalt silicide processing, that can otherwise penetrate the pn junction of a transistor source/drain region a lead to reverse-bias diode-leakage currents.
摘要翻译： 提供了在衬底或其晶体管结构上制造硅化物层的方法。 示例性方法包括以下步骤：在具有pn结的基底上沉积金属层。 加热金属层和衬底以使金属与衬底反应并形成硅化物层。 任何未反应的金属被去除。 将衬底和硅化物层加热到穿过pn结的但低于硅化物层的凝聚阈值温度的硅化物层的任何细丝的聚集阈值温度以上。 该方法消除了硅化物细丝，特别是在硅化钴处理中，否则可以将晶体管源极/漏极区域的pn结穿透导向反向偏置二极管漏电流。
-
-
-
-
-
-
-
-
-
搜索结果
134 条记录 (耗时 0.024 秒)
