公开(公告)号：US20070256065A1

公开(公告)日：2007-11-01

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

公开(公告)号：US07185176B2

公开(公告)日：2007-02-27

申请号：US10449788

申请日：2003-06-02

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

IPC分类号： G06F15/80

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。

公开(公告)号：US06904404B1

公开(公告)日：2005-06-07

申请号：US09227189

申请日：1999-01-08

申请人： Takeshi Norimatsu ,  Shuji Miyasaka ,  Yoshihisa Nakatoh ,  Mineo Tsushima ,  Tomokazu Ishikawa

发明人： Takeshi Norimatsu ,  Shuji Miyasaka ,  Yoshihisa Nakatoh ,  Mineo Tsushima ,  Tomokazu Ishikawa

IPC分类号： G10L19/00 ,  G10L21/02

CPC分类号： G10L19/032 ,  G10L19/0212 ,  G10L19/038

摘要： With respect to audio signal coding and decoding apparatuses, there is provided a coding apparatus that enables a decoding apparatus to reproduce an audio signal even through it does not use all of data from the coding apparatus, and a decoding apparatus corresponding to the coding apparatus. A quantization unit constituting a coding apparatus includes a first sub-quantization unit comprising sub-quantization units for low-band, intermediate-band, and high-band; a second sub-quantization unit for quantizing quantization errors from the first sub-quantization unit; and a third sub-quantization unit for quantizing quantization errors which have been processed by the first sub-quantization unit and the second sub-quantization unit.

公开(公告)号：US06904089B1

公开(公告)日：2005-06-07

申请号：US09472401

申请日：1999-12-27

申请人： Masahiro Sueyoshi ,  Masaharu Matsumoto ,  Kazutaka Abe ,  Kousuke Nishio ,  Takashi Katayama ,  Akihisa Kawamura ,  Shuji Miyasaka ,  Takeshi Fujita

发明人： Masahiro Sueyoshi ,  Masaharu Matsumoto ,  Kazutaka Abe ,  Kousuke Nishio ,  Takashi Katayama ,  Akihisa Kawamura ,  Shuji Miyasaka ,  Takeshi Fujita

IPC分类号： G10L19/022 ,  G10L19/16 ,  H04B1/00 ,  H04B1/66 ,  H04N21/233 ,  H04N21/439

CPC分类号： H04N21/4392 ,  G10L19/022 ,  G10L19/167 ,  H04N21/233

摘要： An encoding device includes an encoding section for generating hit streams having a variable frame length from an input audio signal, a maximum frame length of the bit streams being fixed; a storage section for storing the bit streams generated by the encoding section; and a transfer section for transferring the bit streams at a prescribed transfer rate. The storage section includes a buffer having a capacity corresponding to at least a value which is obtained by subtracting an amount of the bit streams transferable in one frame time period at a minimum possible transfer rate from a value of twice the maximum frame length.

摘要翻译： 编码装置包括编码部分，用于从输入音频信号产生具有可变帧长度的命中流，所述比特流的最大帧长度被固定; 存储部，用于存储由编码部生成的比特流; 以及用于以规定的传送速率传送比特流的传送部分。 存储部分包括缓冲器，其具有对应于至少一个值的缓冲器，该值通过从最大帧长度的两倍的值以最小可能传送速率减去在一个帧时间段中可传送的比特流的量而获得的值。

公开(公告)号：US06631352B1

公开(公告)日：2003-10-07

申请号：US09476897

申请日：2000-01-03

申请人： Takeshi Fujita ,  Takashi Katayama ,  Masahiro Sueyoshi ,  Shuji Miyasaka ,  Masaharu Matsumoto ,  Akihisa Kawamura ,  Kazutaka Abe ,  Kousuke Nishio

发明人： Takeshi Fujita ,  Takashi Katayama ,  Masahiro Sueyoshi ,  Shuji Miyasaka ,  Masaharu Matsumoto ,  Akihisa Kawamura ,  Kazutaka Abe ,  Kousuke Nishio

IPC分类号： G10L2100

CPC分类号： G10L19/167 ,  G11B20/10527

摘要： A decoding circuit, for receiving a bit stream including an encoded audio signal and header information used for-decoding the encoded audio signal, and decoding the encoded audio signal based on the header information, includes a header analysis section for outputting at least one decoding parameter obtained from the header information and decoding parameter change information indicating whether or not the at least one decoding parameter has been changed; a signal processing section for decoding the encoded audio signal, based on the at least one decoding parameter, into a decoded signal and outputting the decoded signal; an automatic mute processing section for executing automatic mute on the decoded signal after the at least one decoding parameter is changed; and an output section for outputting the decoded signal output from the automatic mute processing section.

摘要翻译： 一种解码电路，用于接收包括编码音频信号的位流和用于解码编码音频信号的标题信息，以及基于标题信息对编码音频信号进行解码的标题分析部分，用于输出至少一个解码参数 从表示是否已经改变了至少一个解码参数的标题信息和解码参数改变信息获得; 信号处理部分，用于将编码音频信号基于至少一个解码参数解码为解码信号并输出​​解码信号; 自动静音处理部分，用于在所述至少一个解码参数改变之后对所述解码信号执行自动静音; 以及输出部分，用于输出从自动静音处理部分输出的解码信号。

公开(公告)号：US06546105B1

公开(公告)日：2003-04-08

申请号：US09431092

申请日：1999-11-01

申请人： Takashi Katayama ,  Masaharu Matsumoto ,  Masahiro Sueyoshi ,  Shuji Miyasaka ,  Takeshi Fujita ,  Akihisa Kawamura ,  Kazutaka Abe ,  Kousuke Nishio

发明人： Takashi Katayama ,  Masaharu Matsumoto ,  Masahiro Sueyoshi ,  Shuji Miyasaka ,  Takeshi Fujita ,  Akihisa Kawamura ,  Kazutaka Abe ,  Kousuke Nishio

IPC分类号： H04R500

CPC分类号： H04R5/00

摘要： A sound image localization apparatus comprises a signal source for outputting an audio signal; a localization angle input unit for receiving an angle of a sound image to be localized; a coefficient control unit for receiving sound image localization angle information from the localization angle input unit, reading coefficients from a coefficient memory in accordance with the information, and outputting the coefficients; first, second, and third multipliers for multiplying the audio signal output from the signal source by using first, second, and third coefficients output from the coefficient control means, respectively; a first signal processing unit for receiving the output from the second multiplier, and processing it by using a filter having a predetermined first frequency response; a second signal processing unit for receiving the output from the second multiplier, and processing it by using a filter having a predetermined second frequency response; a first adder for adding the output from the first multiplier and the output from the first signal processing unit to output the sum; a second adder for adding the output from the third multiplier and the output from the second signal processing unit to output the sum; a first output unit for outputting the output of the first adder; and a second output unit for outputting the output of the second adder.

摘要翻译： 声像定位装置包括用于输出音频信号的信号源; 定位角输入单元，用于接收要定位的声像的角度; 系数控制单元，用于从定位角输入单元接收声像定位角度信息，根据该信息从系数存储器读取系数，并输出系数; 第一，第二和第三乘法器，分别通过使用从系数控制装置输出的第一，第二和第三系数来乘以从信号源输出的音频信号; 第一信号处理单元，用于接收来自第二乘法器的输出，并通过使用具有预定的第一频率响应的滤波器对其进行处理; 第二信号处理单元，用于接收来自第二乘法器的输出，并通过使用具有预定的第二频率响应的滤波器进行处理; 第一加法器，用于将来自第一乘法器的输出和来自第一信号处理单元的输出相加以输出和; 第二加法器，用于将来自第三乘法器的输出和来自第二信号处理单元的输出相加以输出和; 第一输出单元，用于输出第一加法器的输出; 以及第二输出单元，用于输出第二加法器的输出。

公开(公告)号：US06304890B1

公开(公告)日：2001-10-16

申请号：US09244155

申请日：1999-02-03

申请人： Shuji Miyasaka ,  Takeshi Fujita ,  Masahiro Sueyoshi ,  Akihisa Kawamura ,  Masaharu Matsumoto ,  Takashi Katayama ,  Kazutaka Abe ,  Kosuke Nishio

发明人： Shuji Miyasaka ,  Takeshi Fujita ,  Masahiro Sueyoshi ,  Akihisa Kawamura ,  Masaharu Matsumoto ,  Takashi Katayama ,  Kazutaka Abe ,  Kosuke Nishio

IPC分类号： G06F738

CPC分类号： G06F7/552 ,  G10L19/0212

摘要： A device of the present invention is an exponential calculation device for calculating x{circumflex over ( )}(a/b) (where a and b are each an integer constant) for a given input value of x. The device includes: an input control section for outputting a value of x′, wherein x′=x when x≦A (where A is a threshold value within a variable range of x) and x′=x/2{circumflex over ( )}b when x>A; a core section for outputting a value of z′=x′{circumflex over ( )}(a/b); and an output control section for outputting a value of z, wherein z=z′ when x≦A and z=z′*2{circumflex over ( )}a when x>A.

摘要翻译： 本发明的装置是用于为x的给定输入值计算x {circumflex over（）}（a / b）（其中a和b各自为整数常数）的指数计算装置。 该装置包括：用于输出x'的值的输入控制部分，其中当x <= A时，x'= x（其中A是x的可变范围内的阈值），x'= x / 2 （）} b当x> A时; 用于输出z'= x'{circumflex over（）}（a / b）的值的核心部分; 以及输出控制部分，用于输出z的值，其中当x> A时z = z'，当x> A时，z = z'* 2 {circumflex over（）} a。

公开(公告)号：US06297754B1

公开(公告)日：2001-10-02

申请号：US09538674

申请日：2000-03-30

申请人： Shuji Miyasaka ,  Takeshi Fujita ,  Masahiro Sueyoshi ,  Akihisa Kawamura ,  Masaharu Matsumoto ,  Takashi Katayama ,  Kazutaka Abe ,  Kousuke Nishio

发明人： Shuji Miyasaka ,  Takeshi Fujita ,  Masahiro Sueyoshi ,  Akihisa Kawamura ,  Masaharu Matsumoto ,  Takashi Katayama ,  Kazutaka Abe ,  Kousuke Nishio

IPC分类号： H03M740

CPC分类号： H03M7/425

摘要： A decoding device for decoding a data stream includes a decoding table including a first region and a second region; a first decoder; and a second decoder. The first region defines a relationship between first data having a predetermined number of bits and a result of decoding a portion of the first data having bits smaller than or equal to the predetermined number. The second region defines a relationship between concatenated data obtained by concatenating the first data with second data having additional bits and a result of decoding the concatenated data. The first decoder reads the first data from the data stream; decodes the portion of the first data based on the first region; determines whether the decoding of the portion of the first data is completed or not; and when the decoding of the portion of the first data is completed, outputs a result of the decoding of the portion of the first data. When the decoding of the portion of the first data is not completed, the second decoder reads the second data out of the data stream; concatenates the first data with the second data to generate the concatenated data; decodes the concatenated data based on the second region; and outputs a result of the decoding of the concatenated data.

摘要翻译： 用于对数据流进行解码的解码装置包括：包括第一区域和第二区域的解码表; 第一解码器; 和第二解码器。 第一区域定义具有预定位数的第一数据和对具有小于或等于预定数目的位的第一数据的一部分进行解码的结果之间的关系。 第二区域定义了通过将第一数据与具有附加位的第二数据连接获得的级联数据和对级联数据进行解码的结果之间的关系。 第一解码器从数据流读取第一数据; 基于第一区域对第一数据的部分进行解码; 确定第一数据的部分的解码是否完成; 并且当第一数据的部分的解码完成时，输出第一数据的部分的解码结果。 当第一数据的部分的解码未完成时，第二解码器从数据流中读出第二数据; 将第一数据与第二数据连接以生成级联数据; 基于第二区域解码连接的数据; 并输出级联数据的解码结果。

公开(公告)号：US08694326B2

公开(公告)日：2014-04-08

申请号：US13590243

申请日：2012-08-21

申请人： Shuji Miyasaka ,  Kosuke Nishio ,  Ichiro Kawashima

发明人： Shuji Miyasaka ,  Kosuke Nishio ,  Ichiro Kawashima

IPC分类号： G10L21/00 ,  H04B1/38 ,  H04M1/00 ,  H04M3/42 ,  H04M9/08 ,  G06F3/00 ,  G06F15/16 ,  G06F11/00

CPC分类号： H04M9/082 ,  H04B3/23

摘要： A communication terminal includes a decoder which decodes an input bitstream received from another communication terminal, to generate an output audio signal and outputs the generated output audio signal to a speaker; and an echo canceller which obtains an input audio signal representing sound captured by a microphone placed in a space to which the speaker outputs the sound, and removes, for respective subbands, an echo component included in the obtained input audio signal and corresponding to the output audio signal, to generate an audio signal for transmission. An encoder codes the audio signal for transmission to generate an output bitstream and transmits the generated output bitstream to another communication terminal; and a control unit controls, for the respective subbands, echo cancellation processing according to a reproduction band of at least one of the output audio signal and the audio signal for transmission.

摘要翻译： 通信终端包括解码器，其对从另一通信终端接收的输入比特流进行解码，以产生输出音频信号，并将所生成的输出音频信号输出到扬声器; 以及回波消除器，其获得表示放置在扬声器输出声音的空间中的麦克风捕获的声音的输入音频信号，并且针对各个子带去除包含在所获得的输入音频信号中并对应于输出的回波分量 音频信号，以产生用于传输的音频信号。 编码器对音频信号进行编码以进行传输以产生输出比特流，并将生成的输出比特流发送到另一通信终端; 并且控制单元根据输出音频信号和音频信号中的至少一个的再现频带对各个子带进行回波消除处理，以进行传输。

公开(公告)号：US07984243B2

公开(公告)日：2011-07-19

申请号：US10577133

申请日：2004-11-02

申请人： Hazuki Kawai ,  Ryuta Nakanishi ,  Tetsuya Tanaka ,  Shuji Miyasaka

发明人： Hazuki Kawai ,  Ryuta Nakanishi ,  Tetsuya Tanaka ,  Shuji Miyasaka

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/121

摘要： A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.

摘要翻译： 根据本发明的高速缓冲存储器包括：W标志设置单元，其修改指示保存高速缓存的数据单元的每个高速缓存条目的访问顺序的顺序数据，以反映实际的访问顺序;以及替换单元，其选择高速缓存条目 根据修改的订单数据进行替换，并替换高速缓存条目。